EL5281 데이터 시트보기 (PDF) - Intersil
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EL5281 Datasheet PDF : 9 Pages
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EL5281
device. When either input signal falls below the negative
input voltage limit, the parasitic PN junction formed by the
substrate and the base of the PNP will turn on, resulting in a
significant increase of input bias current. If one of the inputs
goes above the positive input voltage limit, the output will still
maintain the correct logic level as long as the other input
stays within the input range. However, the propagation delay
will increase. When both inputs are outside the input voltage
range, the output becomes unpredictable. Large differential
voltages greater than the supply voltage should be avoided
to prevent damages to the input stage. Inputs of unused
channels should not be left floating. They should be driven to
a known state. For example, one input can be tied to ground
and the other input can be connected to some voltage
reference (like ±100mV) to avoid oscillation in the output due
to unwanted output to input feedback.
Input Slew Rate
Most high speed comparators oscillate when the voltage of
one of the inputs is close to or equal to the voltage on the
other input due to noise or undesirable feedback. For clean
output waveform, the input must meet certain minimum slew
rate requirements. In some applications, it may be helpful to
apply some positive feedback (hysteresis) between the
output and the positive input. The hysteresis effectively
causes one comparator's input voltage to move quickly past
the other, thus taking the input out of the region where
oscillation occurs. For the EL5281, the propagation delay
increases when the input slew rate increases for low
overdrive voltages. With high overdrive voltages, the
propagation delay does not change much with the input slew
rate.
Latch Pin Dynamics
The EL5281 contains a “transparent” latch for each channel.
The latch pin is designed to be driven with either a TTL or
CMOS output. When the latch is connected to a logic high
level or left floating, the comparator is transparent and
immediately responds to the changes at the input terminals.
When the latch is switched to a logic low level, the
comparator output remains latched to its value just before
the latch’s high-to-low transition. To guarantee data
retention, the input signal must remain the same state at
least 1ns (hold time) after the latch goes low and at least 2ns
(setup time) before the latch goes low. When the latch goes
high, the new data will appear at the output in approximately
6ns (latch propagation delay).
Hysteresis
Hysteresis can be added externally. The following two
methods can be used to add hysteresis.
Inverting comparator with hysteresis:
VREF
R3
R2
+
R1 VIN
-
R3 adds a portion of the output to the threshold set by R1
and R2. The calculation of the resistor values are as follows:
Select the threshold voltage VTH and calculate R1 and R2.
The current through R1/R2 bias string must be many times
greater than the input bias current of the comparator:
VTH
=
VREF
×
-------R-----1--------
R1 + R2
Let the hysteresis be VH, and calculate R3:
R3
=
V-----O--
VH
×
(R1
||
R2
)
where:
VO=VSD-0.8V (swing of the output)
Recalculate R2 to maintain the same value of VTH:
R21
=
(VREF
–
VTH
)
÷
-V----T---H---
R1
+
V-----T---H------–----0----.-5----V----S----D--
R3
Non inverting comparator with hysteresis:
R3
R1
VIN
+
VREF
-
R3 adds a portion of the output to the positive input. Note
that the current through R3 should be much greater than the
input bias current in order to minimize errors. The calculation
of the resistor values as follows:
Pick the value of R1. R1 should be small (less than 1kΩ) in
order to minimize the propagation delay time.
Choose the hysteresis VH and calculate R3:
R3
=
(V
SD
–
0.8
)
×
-R----1--
VH
Check the current through R3 and make sure that it is much
greater than the input bias current as follows:
I = 0----.--5---V-----S----D-----–----V-----R----E----F-
R3
8
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