EL5325 데이터 시트보기 (PDF) - Intersil

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EL5325

12-Channel TFT-LCD Reference Voltage Generator

Intersil 

EL5325

Absolute Maximum Ratings (TA = 25°C)

Supply Voltage between VS & GND . . . . . . 4.5V (min) to 18V (max)

Supply Voltage between VSD & GND . 3V (min) to VS and 7V (max)

Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are

at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

Electrical Specifications VS = 15V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5kΩ and CL = 200pF to 0V, TA = 25°C, unless otherwise

specified.

PARAMETER

DESCRIPTION

CONDITIONS

MIN TYP MAX UNIT

SUPPLY

IS

ISD

ANALOG

Supply Current

Digital Supply Current

No load

10.2 12.5

mA

0.17 0.35

mA

VOL

VOH

ISC

PSRR

tD

VAC

∆VMIS

VDROOP

RINH

REG

CAP

Output Swing Low

Output Swing High

Short Circuit Current

Power Supply Rejection Ratio

Program to Out Delay

Accuracy referred to the ideal value

Channel to Channel Mismatch

Droop Voltage

Input Resistance @ VREFH, VREFL

Load Regulation

Band Gap

Sinking 5mA (VREFH = 15V, VREFL = 0)

Sourcing 5mA (VREFH = 15V, VREFL = 0)

RL = 10Ω

VS+ is moved from 14V to 16V

Code = 512

Code = 512

IOUT = 5mA step

By pass with 0.1µF

14.85

100

45

1

50

14.95

140

65

4

20

2

1

32

0.5

1.3

150

mV

V

mA

dB

ms

mV

mV

2 mV/ms

kΩ

1.5 mV/mA

1.6

V

DIGITAL

VIH

FCLK

VIL

tS

tH

tLC

tCE

tDCO

RSDIN

TPULSE

Duty Cycle

Logic 1 Input Voltage

Clock Frequency

VSD = 5V

VSD = 3.3V

Logic 0 Input Voltage

Setup Time

VSD = 3.3V/5V

Hold Time

Load to Clock Time

Clock to Load Line

Clock to Out Delay Time

Negative edge of SCLK

SDIN Input Resistance

Minimum Pulse Width for EXT_OSC Signal

Duty Cycle for EXT_OSC Signal

4

V

2

V

5

MHz

1

V

20

ns

20

ns

20

ns

20

ns

10

ns

1

GΩ

5

µs

50

%

INL

Integral Nonlinearity Error

1.3

LSB

DNL

Differential Nonlinearity Error

0.5

LSB

F_OSC

Internal Refresh Oscillator Frequency

OSC_Select = 0

21

kHz

2

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