EL5325AIRZ-T13(2004) 데이터 시트보기 (PDF) - Intersil

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EL5325AIRZ-T13
(Rev.:2004)

12-Channel TFT-LCD Reference Voltage Generator with External Shutdown

Intersil 

Typical Performance Curves (Continued)

M=400µs/DIV

5V

0V

5V

0V

200mV

SCLK

SDA

OUTPUT

EL5325A

0V

M=400µs/DIV

OUTPUT

SCLK

SDA

FIGURE 7. SMALL SIGNAL RESPONSE (RISING FROM 0V

TO 200mV)

FIGURE 8. SMALL SIGNAL RESPONSE (FALLING FROM

200mV TO 0V)

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.9

833mW

0.8

0.7

0.6

0.5

θJA =1T2S0S°OCP/W28

0.4

0.3

0.2

0.1

0

0

25

50

75 85 100

125

AMBIENT TEMPERATURE (°C)

FIGURE 9. POWER DISSIPATION vs AMBIENT

TEMPERATURE

General Description

The EL5325A provides a versatile method of providing the

reference voltages that are used in setting the transfer

characteristics of LCD display panels. The V/T

(Voltage/Transmission) curve of the LCD panel requires that

a correction is applied to make it linear; however, if the panel

is to be used in more than one application, the final curve

may differ for different applications. By using the EL5325A,

the V/T curve can be changed to optimize its characteristics

according to the required application of the display product.

Each of the eight reference voltage outputs can be set with a

10-bit resolution. These outputs can be driven to within

50mV of the power rails of the EL5325A. As all of the output

buffers are identical, it is also possible to use the EL5325A

for applications other than LCDs where multiple voltage

references are required that can be set to 10 bit accuracy.

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1.4

1.333W

1.2

1

0.8

θJA =7T5S°SCO/WP28

0.6

0.4

0.2

0

0

25

50

75 85 100

125

AMBIENT TEMPERATURE (°C)

FIGURE 10. POWER DISSIPATION vs AMBIENT

TEMPERATURE

Digital Interface

The EL5325A uses a simple 3-wire SPI compliant digital

interface to program the outputs. The EL5325A can support

the clock rate up to 5MHz.

Serial Interface

The EL5325A is programmed through a three-wire serial

interface. The start and stop conditions are defined by the

ENA signal. While the ENA is low, the data on the SDI (serial

data input) pin is shifted into the 16-bit shift register on the

positive edge of the SCLK (serial clock) signal. The MSB (bit

15) is loaded first and the LSB (bit 0) is loaded last (see

Table 1). After the full 16-bit data has been loaded, the ENA

is pulled high and the addressed output channel is updated.

The SCLK is disabled internally when the ENA is high. The

SCLK must be low before the ENA is pulled low.

5

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