EL7457CS 데이터 시트보기 (PDF) - Elantec -> Intersil

부품명

상세내역

제조사

EL7457CS

40MHz Non-Inverting Quad CMOS Driver

Elantec -> Intersil 

EL7457C

40MHz Non-Inverting Quad CMOS Driver

Application Information:

Product Description

The EL7457C is a high performance 40MHz ultra-high

speed quad driver. Each channel of the EL7457C con-

sists of a single P-channel high side driver and a single

N-channel low side driver. These 3Ω devices will pull

the output (OUTX) to either the high or low voltage, on

VH and VL respectively, depending on the input logic

signal (INX). It should be noted that there is only one set

of high and low voltage pins.

A common output enable (OE) pin is available on the

EL7457C. This pin, when pulled low will put all outputs

in to the high impedance state.

The EL7457C is available in both the 16-pin SOIC and

the space saving 16-pin QSOP packages. The relevant

package should be chosen depending on the calculated

power dissipation.

Supply Voltage Range and Input Compatibility

The EL7457C is designed for operation on supplies from

5V to 15V with 10% tolerance (i.e. 4.5V to 16.5V). The

table on page 6 shows the specifications for the relation-

ship between the VS+, VS-, VH, VL and GND pins. The

EL7457C does not contain a true analog switch and

therefore VL should always be less than VH.

All input pins are compatible with both 3V and 5V

CMOS signals With a positive supply (VS+) of 5V, the

EL7457C is also compatible with TTL inputs.

Power Supply Bypassing

When using the EL7457C, it is very important to use

adequate power supply bypassing. The high switching

currents developed by the EL7457C necessitate the use

of a bypass capacitor on both the positive and negative

supplies. It is recommended that a 4.7µF tantalum

capacitor be used in parallel with a 0.1µF low-induc-

tance ceramic MLC capacitor. These should be placed as

close to the supply pins as possible. It is also recom-

mended that the VH and VL pins have some level of

bypassing, especially if the EL7457C is driving highly

capacitive loads.

Power Dissipation Calculation

When switching at high speeds, or driving heavy loads,

the EL7457C drive capability is limited by the rise in die

temperature brought about by internal power dissipation.

For reliable operation die temperature must be kept

below Tjmax (125°C). It is necessary to calculate the

power dissipation for a given application prior to select-

ing the package type.

Power dissipation may be calculated:

4

∑ PD = (VS × IS) + (CINT × VS2 × f) + (CL × VO2 UT × f)

1

where:

• VS is the total power supply to the EL7457C (from

VS+ to VS-),

• Vout is the swing on the output (VH - VL),

• CL is the load capacitance,

• CINT is the internal load capacitance (50pF max.),

• IS is the quiescent supply current (3mA max.) and

• f is frequency

Having obtained the application’s power dissipation, a

maximum package thermal coefficient may be deter-

mined, to maintain the internal die temperature below

Tjmax.

θja

=

(---T----j--m----a---x----–----T----m-----a---x---)

PD

where:

• Tjmax is the maximum junction temperature (125°C),

• Tmax is the maximum operating temperature,

• PD is the power dissipation calculated above.

Using the value of θja, a suitable package for the applica-

tion may be selected.

In applications with a θja greater than 158°C/W, a 16-pin

QSOP may be used. A 16-pin SOIC is suitable for appli-

cations with a θja value greater than 110°C/W. However,

10

Share Link: