EL7554(2005) 데이터 시트보기 (PDF) - Intersil
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EL7554 Datasheet PDF : 14 Pages
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EL7554
allows 100% turn-on of the upper PFET switch, achieving
VO close to VIN. The maximum achievable VO is:
VO = VIN – (RL + RDSON1) × IO
Where RL is the DC resistance on the inductor and RDSON1
is the PFET on-resistance, nominal 35mΩ at room
temperature with tempco of 0.2mΩ/°C.
Output Voltage Selection
The output voltage can be as high as the input voltage minus
the PMOS and inductor voltage drops. Use R1 and R2 to set
the output voltage according to the following formula:
VO
=
0.8
×
1
+
R-R----12-
Standard values of R1 and R2 are listed in Table 1.
TABLE 1.
VO (V)
0.8
R1 (kΩ)
2
R2 (kΩ)
Open
1
2.49
10
1.2
4.99
10
1.5
10
11.5
1.8
12.7
10.2
2.5
21.5
10
3.3
36
11.5
Voltage Margining
The EL7554 has built-in 5% load stress test (commonly
called voltage margining) function. Combinations of TM and
SEL set the margins shown in Table 2. When this function is
not used, both pins should be connected to SGND, either
directly or through a 10kΩ resister. Figure 16 shows this
feature.
TABLE 2.
CONDITION
TM
Normal
0
SEL
VO
X
Nominal
High Margin
1
1
Nominal + 5%
Low Margin
1
0
Nominal - 5%
Switching Frequency
The regulator operates from 200kHz to 1MHz. The switching
frequency is generated by a relaxation comparator and
adjusted by a COSC. The triangle waveform has 95% duty
ratio and runs from 0.2V to 1.2V. Please refer to Figure 6 for
a specific frequency.
When external synchronization is required, use the following
circuit for connection. Always choose the converter self-
switching frequency 20% lower than the sync frequency to
accommodate component variations.
EL7554
COSC
100pF
EXTERNAL SYNC
SOURCE
FIGURE 20. EXTERNAL SYNC CIRCUIT
Thermal Protection and Junction Temperature
Indicator
An internal temperature sensor continuously monitors the
junction temperature. In the event that the junction
temperature exceeds 135°C, the regulator is in a fault
condition and will shut down. When the temperature falls
back below 110°C, the regulator goes through the soft-start
procedure again.
The VTJ pin is an accurate indicator of the internal silicon
junction temperature TJ, which can be determined by the
following formula. This saves engineering time.
TJ
=
75 + 1----.--2----–-----V----T----J-
0.00384
where VTJ is the voltage at VTJ pin.
Under-Voltage Lockout (UVLO)
When VDD falls bellow 2.5V, the regulator shuts down. When
VDD rises above 2.8V, converter goes through soft-start
process again.
Power Good Indicator (PG) and Over-Voltage
Protection
When the output reaches 10% of the preset voltage, the PG
pin outputs a HI signal as shown in the start-up waveform
(Figure 12). If the output voltage is higher than 10% of the
preset value for any reason, PG will go low and the regulator
will shut down. In addition to the indication power is good,
the PG pin can be used for multiple regulators’ start-up
control as described in the next section.
Full Start-Up Control
The EL7554 offers full start-up control. The core of this
control is a start-up comparator in front of the main PWM
controller. The STP and STN are the inputs to the
comparator, whose HI output forces the PWM comparator to
skip switching cycles. The user can choose any of the
following control configurations:
1. ADJUSTABLE SOFT-START
In this configuration, the ramp-up time is adjustable to any
time longer than the building soft-start time of 2ms. The
approximate ramp-up time, TST, is:
TST
=
R
C
V-V----I-O-N--
10
FN7360.2
January 31, 2005
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