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EPM5064-35

Programmable Logic Device Family

Altera Corporation 

MAX 5000 Programmable Logic Device Family Data Sheet

Table 3. MAX 5000 Pin Count & Package Options Note (1)

Device

EPM5032

EPM5064

EPM5128

EPM5130

EPM5192

28

CerDIP

PDIP

JLCC

PLCC

SOIC

Pin Count

44

68

84

JLCC

PLCC

JLCC

PLCC

PGA

JLCC

PLCC

JLCC

PLCC

PGA

100

PGA

PQFP

Note:

(1) Contact Altera for up to date information on package availability.

MAX 5000 EPLDs have between 32 and 192 macrocells that are combined

into groups called logic array blocks (LABs). Each macrocell has a

programmable-AND/fixed-OR array and a configurable register that

provides D, T, JK, or SR operation with independent programmable clock,

clear, and preset functions. To build complex logic functions, each

macrocell can be supplemented with shareable expander product terms

(“shared expanders”) to provide more than 32 product terms per

macrocell.

The MAX 5000 family is supported by Altera’s MAX+PLUS II

development system, a single, integrated package that offers schematic,

text—including the Altera Hardware Description Language (AHDL)—

and waveform design entry; compilation and logic synthesis; simulation

and timing analysis; and device programming. MAX+PLUS II provides

EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for

additional design entry and simulation support from other industry-

standard PC- and workstation-based EDA tools. MAX+PLUS II runs on

486- and Pentium-based PCs, and Sun SPARCstation, HP 9000 Series 700,

IBM RISC System/6000 workstations.

f For more information, go to the MAX+PLUS II Programmable Logic

Development System & Software Data Sheet in this data book.

Altera Corporation

313

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