Q67100-H3223 데이터 시트보기 (PDF) - Infineon Technologies

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Q67100-H3223

4 Kbit (512 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus

Infineon Technologies 

SLx 24C04

4

Device Addressing and EEPROM Addressing

After a START condition, the master always transmits a Command Byte CSW or CSR.

After the acknowledge of the EEPROM a Control Byte follows, its content and the

transmitter depend on the previous Command Byte. The description of the Command

and Control Bytes is shown in table 2.

Command Byte

Control Byte

Selects operation: the least significant bit b0 is low for a write

operation (Chip Select Write Command Byte CSW) or set high for a

read operation (Chip Select Read Command Byte CSR).

Contains address information: in the CSW Command Byte, the

bit position b1 is decoded for the uppermost EEPROM address bit

A8 (in the CSR Command Byte, the bit positions b3 to b1 are left

undefined, in the CSW Command Byte, the bit positions b3 and b2

as well).

Following CSW (b0 = 0): contains the eight lower bits of the

EEPROM address (EEA) bit A7 to A0.

Following CSR (b0 = 1): contains the data read out, transmitted by

the EEPROM. The EEPROM data are read as long as the master

pulls down SDA after each byte in order to acknowledge the

transfer. The read operation is stopped by the master by releasing

SDA (no acknowledge is applied) followed by a STOP condition.

Table 2

Command and Control Byte for I2C-Bus Addressing of Chip and EEPROM

CSW

CSR

EEA

Definition

Function

b7 b6 b5 b4 b3 b2 b1 b0

1 0 1 0 x x A8 0 Chip Select for Write

1 0 1 0 x x x 1 Chip Select for Read

A7 A6 A5 A4 A3 A2 A1 A0 EEPROM address

The device has an internal address counter which points to the current EEPROM

address.

The address counter is incremented

– after a data byte to be written has been acknowledged, during entry of further data

byte

– during a byte read, thus the address counter points to the following address after

reading a data byte.

Semiconductor Group

9

1998-07-27

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