FAN6755 데이터 시트보기 (PDF) - Fairchild Semiconductor

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FAN6755

Highly Integrated Green-Mode PWM Controller

Fairchild Semiconductor 

Functional Description

Startup Current

For startup, the HV pin is connected to the line input

(1N4007 / 100KΩ recommended) or bulk capacitor

through a resistor, RHV. Startup current drawn from pin

HV (typically 3.5mA) charges the hold-up capacitor

through the diode and resistor. When the VDD capacitor

level reaches VDD-ON, the startup current switches off. At

this moment, the VDD capacitor only supplies the

FAN6755 to maintain VDD before the auxiliary winding of

the main transformer to provide the operating current.

Operating Current

Operating current is around 2mA. The low operating

current enables better efficiency and reduces the

requirement of VDD hold-up capacitance.

Green-Mode Operation

The proprietary green-mode function provides an off-

time modulation to reduce the switching frequency in

light-load and no-load conditions. The on time is limited

for better abnormal or brownout protection. VFB, which is

derived from the voltage feedback loop, is taken as the

reference. Once VFB is lower than the threshold voltage,

switching frequency is continuously decreased to the

minimum green-mode frequency of around 23KHz.

Current Sensing / PWM Current Limiting

Peak-current-mode control is utilized to regulate output

voltage and provide pulse-by-pulse current limiting. The

switch current is detected by a sense resistor into the

SENSE pin. The PWM duty cycle is determined by this

current sense signal and VFB, the feedback voltage.

When the voltage on the SENSE pin reaches around

VCOMP=(VFB–0.6)/4, a switch cycle is terminated

immediately. VCOMP is internally clamped to a variable

voltage around 0.83V for output power limit.

Gate Output / Soft Driving

The BiCMOS output stage is a fast totem-pole gate

driver. Cross conduction has been avoided to minimize

heat dissipation, increase efficiency, and enhance

reliability. The output driver is clamped by an internal

18V Zener diode to protect power MOSFET transistors

against undesirable gate over voltage. A soft driving

waveform is implemented to minimize EMI.

Soft-Start

For many applications, it is necessary to minimize the

inrush current at startup. The built-in 5.5ms soft-start

circuit significantly reduces the startup current spike

and output voltage overshoot.

Slope Compensation

The sensed voltage across the current-sense resistor is

used for peak-current-mode control and pulse-by-pulse

current limiting. Built-in slope compensation improves

stability and prevents sub-harmonic oscillation.

FAN6755 inserts a synchronized positive-going ramp at

every switching cycle.

Constant Output Power Limit

For constant output power limit over universal input-

voltage range, the peak-current threshold is adjusted by

the voltage of the VIN pin. Since the VIN pin is

connected to the rectified AC input line voltage through

the resistive divider, a higher line voltage generates a

higher VIN voltage. The threshold voltage decreases as

VIN increases, making the maximum output power at

high-line input voltage equal to that at low-line input.

The value of R-C network should not be so large that it

affects the power limit (shown in Figure 21). Usually, R

and C should be less than 100Ω and 470pF,

respectively.

Leading-Edge Blanking (LEB)

Each time the power MOSFET is switched on, a turn-on

spike occurs on the sense resistor. To avoid premature

termination of the switching pulse, a leading-edge

blanking time is built in. During this blanking period, the

current-limit comparator is disabled and cannot switch

off the gate driver.

Under-Voltage Lockout (UVLO)

The turn-on and turn-off thresholds are fixed internally

at 16V and 7.8V in normal mode. During startup, the

hold-up capacitor must be charged to 16V through the

startup resistor to enable the IC. The hold-up capacitor

continues to supply VDD before the energy can be

delivered from auxiliary winding of the main transformer.

VDD must not drop below 7.8V during startup. This

UVLO hysteresis window ensures that the hold-up

capacitor is adequate to supply VDD during startup.

Figure 21. Current-Sense R-C Filter

© 2009 Fairchild Semiconductor Corporation

FAN6755 • Rev. 1.0.1

11

www.fairchildsemi.com

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