AS4LC4M4883C 데이터 시트보기 (PDF) - Austin Semiconductor

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AS4LC4M4883C

4 MEG x 4 DRAM 3.3V, EDO PAGE MODE

Austin Semiconductor 

AUSTIN SEMICONDUCTOR, INC.

AS4LC4M4 883C

4 MEG x 4 DRAM

REFRESH

Preserve correct memory cell data by maintaining power and executing a ?R?A/S cycle (READ, WRITE) or ?R?A/S refresh cycle

(?R?A/S ONLY, CBR, or HIDDEN) so that all 2,048 combinations of R? ?AS/ addresses are executed at least every 32ms, regardless

of sequence. The CBR REFRESH cycle will invoke the refresh counter for automatic ?R?A/S addressing.

RAS

V IH

V IL

CAS

V IH

V IL

,, ,,, ,,,,, ADDR

V

V

IH

IL

,,,,, , , DQ VVIIOOHL

ROW

COLUMN (A)

OPEN

VALID DATA (A)

t WHZ

WE

V IH

V IL

tWPZ

OE

V IH

V IL

,,,,,, ,,,,, COLUMN(B)

COLUMN (C)

,, ,,,,, VALIDDATA(B)

t WHZ

INPUT DATA (C)

COLUMN (D)

The DQs go to High-Z if WE falls, and if tWPZ is met,

will remain High-Z until CAS goes LOW with

WE HIGH (i.e., until a READ cycle is initiated).

Figure 2

?W/E CONTROL OF DQs

WE may be used to disable the DQs to prepare

for input data in an EARLY WRITE cycle. The DQs

will remain High-Z until CAS goes LOW with

WE HIGH (i.e., until a READ cycle is initiated).

,,DON’T CARE

,,,,UNDEFINED

AS4LC4M4

Rev. 11/97

DS000022

2-75

Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.

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