FDS3992 데이터 시트보기 (PDF) - Fairchild Semiconductor
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FDS3992 Datasheet PDF : 11 Pages
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SABER Electrical Model
REV Aug 2002
template FDS3992 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.4e-12,nl=1.04,rs=13e-3,trs1=2.1e-3,trs2=4.7e-7,cjo=5.5e-10,m=0.57,tt=3.25e-8,xti=4.6)
dp..model dbreakmod = (rs=1.6,trs1=2.4e-3,trs2=-1.0e-5)
dp..model dplcapmod = (cjo=1.6e-10,isl=10e-30,nl=10,m=0.54)
m..model mmedmod = (type=_n,vto=3.8,kp=2.0,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.35,kp=28,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.26,kp=0.04,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-3.0,voff=-2.0)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-3.0) DPLCAP
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=1.0)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=1.0,voff=-1.5) 10
c.ca n12 n8 = 2.3e-10
5
RSLC1
LDRAIN
RLDRAIN
c.cb n15 n14 = 3.5e-10
c.cin n6 n8 = 7.47e-10
RSLC2
51
ISCL
DRAIN
2
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 108
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
GATE
1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
-
LGATE
ESG
6
8
+
EVTHRES
EVTEMP
+ 19 -
8
RGATE + 18 - 6
9
20 22
RLGATE
CIN
50
RDRAIN
16
21
DBREAK
11
MWEAK
MMED
MSTRO
8
EBREAK
+
17
18
-
7
DBODY
LSOURCE
SOURCE
3
i.it n8 n17 = 1
RSOURCE
RLSOURCE
l.lgate n1 n9 = 5.61e-9
l.ldrain n2 n5 = 1e-9
l.lsource n3 n7 = 1.98e-9
S1A
12 13
8
S1B
S2A
14
15
13
S2B
RBREAK
17
18
RVTEMP
res.rlgate n1 n9 = 56.1
CA
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 19.8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
13
+
EGS
6
8
-
CB
+ 14
EDS
5
8
-
19
IT
-
VBAT
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-1e-8
res.rdrain n50 n16 = 25e-3, tc1=1.15e-2,tc2=2.8e-5
res.rgate n9 n20 = 3.7
res.rslc1 n5 n51 = 1e-6, tc1=3.3e-3,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 20e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-4.8e-3,tc2=-1.1e-5
res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=1.5e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/45))** 2.5))
}
©2004 Fairchild Semiconductor Corporation
FDS3992 Rev. B1
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