MC10181L 데이터 시트보기 (PDF) - Motorola => Freescale

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MC10181L

4-Bit Arithmetic Logic Unit/Function Generator

Motorola => Freescale 

MC10181

Characteristic

Propagation Delay

Rise Time, Fall Time

Propagation Delay

Rise Time, Fall Time

Propagation Delay

Rise Time, Fall Time

Symbol

t++,t– –

t+,t–

t++,t+–

t–+,t– –

t+,t–

t++,t+–

t–+,t– –

t+,t–

Input

Cn

Cn

Cn

Cn

Cn

A1

A1

A1

Output

Cn+4

Cn+4

F1

F1

F1

F1

F1

F1

Conditions†

A0,A1,A2,A3

A0,A1,A2,A3

A0

A0

A0

—

—

—

AC Switching Characteristics

–30°C *

+25°C

+85°C *

Min Max Min Typ Max Min Max Unit

1.0 5.1 1.1 3.1 5.0 1.1 5.4 ns

1.0 3.2 1.0 2.0 3.0 1.0 3.2 ns

1.7 7.2 2.0 4.5 7.0 2.0 7.5 ns

1.7 7.2 2.0 4.5 7.0 2.0 7.5 ns

1.3 5.3 1.5 3.0 5.0 1.5 5.3 ns

2.6 10.4 3.0 6.5 10 3.0 10.8 ns

2.6 10.4 3.0 6.5 10 3.0 10.8 ns

1.3 5.4 1.5 3.0 5.0 1.5 5.3 ns

Propagation Delay

Rise Time, Fall Time

Propagation Delay

Rise Time, Fall Time

Propagation Delay

Rise Time, Fall Time

Propagation Delay

Rise Time, Fall Time

Propagation Delay

Rise Time, Fall Time

Propagation Delay

Rise Time, Fall Time

Propagation Delay

Rise Time, Fall Time

Propagation Delay

Rise Time, Fall Time

t++,t– –

t+,t–

t++,t– –

t+,t–

t+–,t–+

t+,t–

t++,t–+

t+,t–

t++,t– –

t+,t–

t++,t– –

t+,t–

t+–,t–+

t+,t–

t++,t+–

t+,t–

A1

PG

A1

PG

S0,S3

S0,S3

1.6 7.0 2.0 5.0 6.5 2.0 7.0 ns

0.8 3.7 1.1 2.0 3.5 1.1 3.8 ns

A1

GG A0,A2,A3,Cn 1.1 7.4 2.0 4.5 7.0 1.3 7.7 ns

A1

GG A0,A2,A3,Cn 1.2 5.1 1.5 4.0 5.0 1.2 5.3 ns

A1 Cn+4 A0,A2,A3,Cn 1.7 7.3 2.0 5.0 7.0 2.0 7.8 ns

A1 Cn+4 A0,A2,A3,Cn 1.0 3.1 1.0 2.0 3.0 1.0 3.2 ns

B1

F1

B1

F1

S3,Cn

S3,Cn

2.7 11.3 3.0 8.0 11 3.0 11.9 ns

1.2 5.3 1.5 3.5 5.0 1.5 5.3 ns

B1

PG

B1

PG

S0,A1

S0,A1

1.6 7.7 2.0 6.0 7.5 2.0 8.0 ns

1.0 3.6 1.1 2.0 3.5 1.1 3.9 ns

B1

GG

B1

GG

S3,Cn

S3,Cn

1.7 8.2 2.0 6.0 8.0 2.0 8.6 ns

1.4 5.2 1.5 3.0 5.0 1.2 5.4 ns

B1 Cn+4

B1 Cn+4

S3,Cn

S3,Cn

1.8 8.2 2.0 6.0 8.0 2.0 8.7 ns

0.9 3.1 1.0 2.0 3.0 1.0 3.2 ns

M

F1

M

F1

—

2.4 10.3 3.0 6.5 10 3.0 10.8 ns

—

1.1 5.1 1.5 4.0 5.0 1.5 5.3 ns

Propagation Delay

t+–,t–+

S1

F1

Rise Time, Fall Time

t+,t–

S1

F1

A1,B1

A1,B1

2.5 10.7 3.0 6.5 10 3.0 10.8 ns

1.0 5.4 1.5 3.0 5.0 1.5 5.4 ns

Propagation Delay

Rise Time, Fall Time

t–+,t+–

S1

PG

t+,t–

S1

PG

Propagation Delay

Rise Time, Fall Time

t+–,t–+

t+,t–

S1 Cn+4

S1 Cn+4

Propagation Delay

Rise Time, Fall Time

t+–,t–+

S1

GG

t+,t–

S1

GG

† Logic high level (+1.11 Vdc) applied to pins listed. All other

input pins are left floating or tied to +0.31 Vdc.

VCC1 = VCC2 = +2.0 Vdc, VEE = –3.2 Vdc

A3,B3

A3,B3

A3,B3

A3,B3

A3,B3

A3,B3

1.7 8.3 2.0 6.0 8.0 2.0 8.4 ns

0.8 5.1 1.1 3.0 5.0 1.1 5.2 ns

1.6 9.3 2.0 6.0 9.0 2.0 9.9 ns

0.9 5.3 1.1 3.0 5.0 1.0 5.2 ns

1.5 9.6 2.0 6.0 9.0 1.9 9.7 ns

0.8 6.2 0.8 3.0 6.0 0.8 6.5 ns

* L Suffix Only

MECL Data

DL122 — Rev 6

3–145

MOTOROLA

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