MC14581BCP 데이터 시트보기 (PDF) - Motorola => Freescale
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MC14581BCP Datasheet PDF : 7 Pages
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ÎÎÎÎSÎÎÎÎWIÎÎÎÎTCHÎÎÎÎINGÎÎÎÎCHÎÎÎÎARÎÎÎÎAChCaÎÎÎÎTrEacRtÎÎÎÎeISriTsÎÎÎÎtIiCcSÎÎÎÎ* (CÎÎÎÎL=5ÎÎÎÎ0pFÎÎÎÎ,TAÎÎÎÎ=2ÎÎÎÎ5_CÎÎÎÎ)SymÎÎÎÎbolÎÎÎÎÎÎÎÎVÎÎÎÎDDÎÎÎÎÎÎÎÎÎÎÎÎMinÎÎÎÎÎÎÎÎTÎÎÎÎypÎÎÎÎ# ÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎUÎÎÎÎnitÎÎÎÎ
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
ns
tTHL
5.0
—
100
200
10
—
50
100
15
—
40
80
Propagation Delay Time
Sum in to Sum Out
tPLH, tPHL = (1.7 ns/pF) CL + 620 ns
tPLH, tPHL = (0.66 ns/pF) CL + 217 ns
tPLH, tPHL = (0.5 ns/pF) CL + 155 ns
tPLH,
ns
tPHL
5.0
—
705
1410
10
—
250
500
15
—
180
360
Sum in to Sum Out (Logic Mode)
tPLH, tPHL = (1.7 ns/pF) CL + 520 ns
tPLH, tPHL = (0.66 ns/pF) CL + 182 ns
tPLH, tPHL = (0.5 ns/pF) CL + 155 ns
tPLH,
ns
tPHL
5.0
—
605
1210
10
—
215
430
15
—
180
360
Sum in to A = B
tPLH, tPHL = (1.7 ns/pF) CL + 870 ns
tPLH, tPHL = (0.66 ns/pF) CL + 297 ns
tPLH, tPHL = (0.5 ns/pF) CL + 220 ns
tPLH,
ns
tPHL
5.0
—
955
1910
10
—
330
660
15
—
245
490
Sum in to P or G
tPLH, tPHL = (1.7 ns/pF) CL + 400 ns
tPLH, tPHL = (0.66 ns/pF) CL + 147 ns
tPLH, tPHL = (0.5 ns/pF) CL + 105 ns
tPLH,
ns
tPHL
5.0
—
485
970
10
—
180
360
15
—
130
260
Sum in to Cn+4
tPLH, tPHL = (1.7 ns/pF) CL + 530 ns
tPLH, tPHL = (0.66 ns/pF) CL + 187 ns
tPLH, tPHL = (0.5 ns/pF) CL + 135 ns
tPLH
ns
5.0
—
615
1230
10
—
220
440
15
—
160
360
Carry in to Sum Out
tPLH, tPHL = (1.7 ns/pF) CL + 295 ns
tPLH, tPHL = (0.66 ns/pF) CL + 112 ns
tPLH, tPHL = (0.5 ns/pF) CL + 80 ns
tPLH,
ns
tPHL
5.0
—
380
760
10
—
145
290
15
—
105
210
Carry in to Cn+4
tPLH, tPHL = (1.7 ns/pF) CL + 220 ns
tPLH, tPHL = (0.66 ns/pF) CL + 87 ns
tPLH, tPHL = (0.5 ns/pF) CL + 60 ns
tPLH,
ns
tPHL
5.0
—
305
610
10
—
120
240
15
—
85
170
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Test
Sumin to Sumout
Delay Time
Sumin to P
Delay Time
Sumin to G
Delay Time
Sumin to Cn+4
Delay Time
Cn to Sumout
Delay Time
Cn to Cn+4
Delay Time
Sumin to A = B
Delay Time
Sumin to Sumout
Delay Time
(Logic Mode)
AC TEST SETUP REFERENCE TABLE
AC Paths
DC Data Inputs
Inputs
A0
Outputs
Any F
To VSS
Remaining A’s
Cn
To VDD
All B’s
A0
P
Remaining A’s
Cn
All B’s
B0
G
All A’s
Cn
Remaining B’s
B0
Cn+y
All A’s
Cn
Remaining B’s
Cn
Any F
All A’s
All B’s
Mode
Add
Add
Add
Add
Add
Fig. 3
Waveform
#1
#1
#1
#2
#1
Cn
Cn+4
All A’s
All B’s
Add
#1
A0
A=B
All B’s
Remaining A’s
Cn
Sub
#2
B0
Any F
All A’s
M
Exclusive
OR
#2
MOTOROLA CMOS LOGIC DATA
MC14581B
3
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