UPD75P3018GC-3B9 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD75P3018GC-3B9

4-BIT SINGLE-CHIP MICROCONTROLLER

NEC => Renesas Technology 

µPD75P3018

3.2 Non-port Pins (1/2)

Pin name

I/O

Shared by

TI0

TI1, TI2

PTO0

PTO1

PTO2

PCL

BUZ

SCK

SO/SB0

Input P13

Input P12/INT2

I/O P20

P21

P22

Output P22

I/O P23

I/O P01

I/O P02

SI/SB1

I/O P03

INT4

Input P00

INT0

Input P10

INT1

INT2

KR0-KR3

KR4-KR7

X1

X2

XT1

XT2

RESET

MD0

MD1

MD2, MD3

D0-D3

D4-D7

VPP

P11

Input P12/TI1/TI2

I/O P60-P63

I/O P70-P73

Input

—

—

Input

—

—

Input

—

I/O P30/LCDCL

P31/SYNC

P32, P33

I/O P40-P43

P50-P53

—

—

VDD

—

—

Vss

—

—

Function

External event pulse input to timer/event counter

Timer/event counter output

Status I/O circuit

after reset typeNote

Input

<B>-C

Input

E-B

Clock output

Frequency output (for buzzer or system clock trimming)

Serial clock I/O

Serial data output

Serial data bus I/O

Serial data input

Serial data bus I/O

Edge detection vectored interrupt input

(valid for detecting both rising and falling edges)

Edge detection vectored interrupt input Clock synch/asynch

(detected edge is selectable)

is selectable

Asynch

Rising edge detection test input

Asynch

Parallel falling edge detection test input

Parallel falling edge detection test input

Ceramic/crystal oscillation circuit connection for main system

clock. If using an external clock, input to X1 and input

inverted phase to X2.

Crystal oscillation circuit connection for subsystem clock.

If using an external clock, input to XT1 and input inverted

phase to XT2. XT1 can be used as a 1-bit (test) input.

System reset input

Mode selection for program memory (PROM) write/verify

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

—

—

—

Input

E-B

E-B

<F>-A

<F>-B

<M>-C

<B>

<B>-C

<B>-C

<F>-A

<F>-A

—

—

<B>

E-B

Data bus for program memory (PROM) write/verify

Input

M-E

Programmable power supply voltage for program memory

—

—

(PROM) write/verify.

For normal operation, connect directly to VDD.

Apply +12.5 V for PROM write/verify.

Positive power supply

—

—

Ground

—

—

Note Circuit types enclosed in brackets indicate Schmitt trigger input.

8

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