LC662316A 데이터 시트보기 (PDF) - SANYO -> Panasonic
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LC662316A
SANYO -> Panasonic
LC662316A Datasheet PDF : 25 Pages
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LC662304A, 662306A, 662308A, 662312A, 662316A
Continued from preceding page.
ROM area
3FFEH
3FFFH
Bit
Option specified
7
6
5
4
Reserved. Must be set to predefined data values.
3
2
1
0
7
6
5
4
Reserved. Must be set to predefined data values.
3
2
1
0
Option/data relationship
This data is generated by the assembler.
If the assembler is not used, set this data to ‘00’.
This data is generated by the assembler.
If the assembler is not used, set this data to ‘00’.
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Symbol
Conditions
Ratings
Unit
Note
Maximum supply voltage
Input voltage
Output voltage
VDD max
VIN1
VDD
P2, P3 (except for the P33/HOLD pin),
P61, and P63
–0.3 to +7.0
V
–0.3 to +12.0
V
1
VIN2
VOUT1
All other inputs
P2, P3 (except for the P33/HOLD pin),
P61, and P63
–0.3 to VDD + 0.3
V
2
–0.3 to +12.0
V
1
VOUT2 All other inputs
–0.3 to VDD + 0.3
V
2
ION1
P0, P1, P2, P3 (except for the P33/HOLD pin),
P4, P5, P6, PC
20
mA
3
Output current per pin
Total pin current
Allowable power dissipation
ION2
–IOP1
–IOP2
–IOP3
Σ ION1
Σ ION2
Σ IOP1
Σ IOP2
Pd max
P41, P43, PC3, PD1, PD3
P0, P1, P4, P5
P2, P3 (except for the P33/HOLD pin), P6, and PC
P41, P43, PC3, PD1, PD3
P0, P1, P2, P3 (except for the P33/HOLD pin), PD
P4, P5, P6, PC
P0, P1, P2, P3 (except for the P33/HOLD pin), PD
P4, P5, P6, PC
Ta = –30 to +70°C: DIP42S (QFP48E)
20
mA
3
2
mA
4
4
mA
4
10
mA
4
75
mA
3
75
mA
3
25
mA
4
25
mA
4
600 (430) mW
5
Operating temperature
Topr
–30 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Note: 1. Applies to pins with open-drain output specifications. For pins with other than open-drain output specifications, the ratings in the pin column for that
pin apply.
2. For the oscillator input and output pins, levels up to the free-running oscillation level are allowed.
3. Sink current (Applies to PD when the inverter array specifications are selected.)
4. Source current (Applies to all pins except PD for which the pull-up output specifications, the CMOS output specifications, or the inverter array
specifications have been selected. Applies to PD pins for which the inverter array specifications have been selected.)
5. We recommend the use of reflow soldering techniques to solder mount QFP packages.
Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering
bath (dip-soldering techniques).
No. 5483-11/25
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