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FSQ0165RN 데이터 시트보기 (PDF) - Fairchild Semiconductor

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FSQ0165RN Datasheet PDF : 21 Pages
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Pin Assignments
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin#
1
Name
GND
2
VCC
3
Vfb
4
Sync
5
6, 7, 8
Vstr
Drain
Description
SenseFET source terminal on primary side and internal control ground.
Positive supply voltage input. Although connected to an auxiliary transformer winding,
current is supplied from pin 5 (Vstr) via an internal switch during startup (see Figure 2).
It is not until VCC reaches the UVLO upper threshold (12V) that the internal startup switch
opens and device power is supplied via the auxiliary transformer winding.
The feedback voltage pin is the non-inverting input to the PWM comparator. It has a
0.9mA current source connected internally while a capacitor and opto-coupler are typically
connected externally. There is a time delay while charging external capacitor Cfb from 3V
to 6V using an internal 5A current source. This delay prevents false triggering under
transient conditions, but still allows the protection mechanism to operate under true
overload conditions.
This pin is internally connected to the sync-detect comparator for valley switching.
Typically the voltage of the auxiliary winding is used as Sync input voltage and external
resistors and capacitor are needed to make delay to match valley point. The threshold of
the internal sync comparator is 0.7V/0.2V.
This pin is connected to the rectified AC line voltage source. At startup, the internal switch
supplies internal bias and charges an external storage capacitor placed between the Vcc
pin and ground. Once the VCC reaches 12V, the internal switch is opened.
The drain pins are designed to connect directly to the primary lead of the transformer and
are capable of switching a maximum of 650V. Minimizing the length of the trace
connecting these pins to the transformer decreases leakage inductance.
© 2007 Fairchild Semiconductor Corporation
FSQ0365, FSQ0265, FSQ0165, FSQ321 • Rev. 1.0.6
4
www.fairchildsemi.com

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