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CA3304(1999) 데이터 시트보기 (PDF) - Intersil

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CA3304
(Rev.:1999)
Intersil
Intersil Intersil
CA3304 Datasheet PDF : 11 Pages
First Prev 11
CA3304, CA3304A
Effective Number of Bits (ENOB)
The effective number of bits (ENOB) is derived from the
SINAD data. ENOB is calculated from:
ENOB = (SINAD - 1.76 + VCORR)/6.02,
where: VCORR = 0.5dB.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the measured input signal.
Operating and Handling Considerations
HANDLING
All inputs and outputs of CMOS devices have a network for
electrostatic protection during handling. Recommended han-
dling practices for CMOS devices are described in
lCAN-6525. “Guide to Better Handling and Operation of
CMOS Integrated Circuits.”
OPERATING
Operating Voltage
During operation near the maximum supply voltage limit, care
should be taken to avoid or suppress power supply turn-on
and turn-off transients, power supply ripple, or ground noise;
any of these conditions must not cause the power supply
voltages to exceed the absolute maximum rating.
Input Signals
To prevent damage to the input protection circuit, input signals
should never be greater than VDD or VAA+ nor less than VSS
or VAA- (depending upon which supply the protection network
is referenced. See Maximum Ratings.). Input currents must
not exceed 20mA even when the power supply is off.
Unused Inputs
A connection must be provided at every input terminal. All
unused input terminals must be connected to either VDD or
VSS, whichever is appropriate.
Output Short Circuits
Shorting of outputs to any supply potential may damage
CMOS devices by exceeding the maximum device dissipation.
+5V
+FULL
SCALE
REF.
BUFFER
INPUT
1K
ADJUST
CENTER
+5V
VAA+ DC
NC
VDD
OF
NC
VREF+ B4
VIN
B3
VREF- B2
VAA- B1
VSS CE1
CLK CE2
CA3304
CLK
VAA+
VDD
VREF +
VIN
VREF -
VAA-
VSS
DC
OF
B4
B3
B2
B1
CE1
CE2
NC
+5V
CA3304
CLOCK
INPUT
B5 MSB
B4
B3
B2
B1
FIGURE 13. TYPICAL CA3304 5-BIT CONFIGURATION
OVERFLOW
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14V15 V16
INPUT VOLTAGE
FIGURE 14. IDEAL TRANSFER CURVE
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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