CA3304(1999) 데이터 시트보기 (PDF) - Intersil
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CA3304 Datasheet PDF : 11 Pages
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CA3304, CA3304A
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME
Bit 1
Bit 2
Bit 3
Bit 4
DC
OF
CE2
VSS
CE1
VAA+
VIN
VREF+
VREF-
VAA-
CLK
VDD
DESCRIPTION
Bit 1 (LSB).
Bit 2.
Bit 3.
Bit 4 (MSB).
Output Data Bits
(High = True)
Data Change.
Overflow.
Three-State Output Enable Input, active low. See the Chip Enable Truth Table.
Digital Ground.
Three-State Output Enable Input, active high. See the Chip Enable Truth Table.
Analog Power Supply, +5V.
Analog Signal Input.
Reference Voltage Positive Input.
Reference Voltage Negative Input.
Analog Ground.
Clock Input.
Digital Power Supply, +5V.
CHIP ENABLE TRUTH TABLE
CE1
0
1
X
X = Don't Care
CE2
BIT 1 - BIT 4
1
Valid
1
Three-State
0
Three-State
TABLE 1. OUTPUT CODE TABLE
DC, OF
Valid
Valid
Three-State
INPUT VOLTAGE (V)
OUTPUT CODE
CODE
DESCRIPTION
Zero
VREF+ = 1V 1.6V
2V
3.2V 4.8V
DECIMAL
VREF- = -1V
0V
0V
0V
0V
OF B4 B3 B2 B1 COUNT
-1.000
0
0
0
0
0
0
0
0
0
0
1 LSB
-0.875
0.1
0.125 0.2
0.3
0
0
0
0
1
1
2 LSB
-0.750
0.2
0.250 0.4
0.6
0
0
0
1
0
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1/2 Full Scale -1 LSB
-0.125
0.7
0.875 1.4
2.1
0
0
1
1
1
7
1/2 Full Scale
0
0.8
1.000 1.6
2.4
0
1
0
0
0
8
1/2 Full Scale +1 LSB
0.125
0.9
1.125 1.8
2.7
0
1
0
0
1
9
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Full Scale -1 LSB
0.750
1.4
1.750 2.8
4.2
0
1
1
1
0
14
Full Scale
0.875
1.5
1.875 3.0
4.5
0
1
1
1
1
15
Overflow
1.000
1.6
2.000 3.2
4.8
1
1
1
1
1
31
Step Size
0.125
0.1
0.125 0.2
0.3
NOTE:
1. The voltages listed are the ideal centers of each output code shown as a function of its associated reference voltage See Ideal Transfer
Curve Figure 6. The output code should exist for an input equal to the ideal center voltage ±1/2 of the step size.
4-10
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