CA3304(1999) 데이터 시트보기 (PDF) - Intersil

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CA3304
(Rev.:1999)

4-Bit, 25 MSPS, Flash A/D Converters

Intersil 

CA3304, CA3304A

Functional Diagram

VIN

11

1/2R

12

VREF +

R

φ2 φ1

φ1

φ1 φ1

VAA+

10

VDD

16

†CAB #16

COUNT

16

DQ

LATCH

16

φ2 OUTPUT

REGISTER

DQ

CLK

DQ

CLK

THREE-STATE

DRIVERS

5

DATA

CHANGE

6 OVERFLOW

DQ

CLK

R

D

COUNT

8

Q

ENCODER

LOGIC

†CAB #8

LATCH

8

ARRAY

DQ

CLK

R

DQ

CLK

4 BIT 4

3 BIT 3

2 BIT 2

R

VREF- 1/2R

13

50kΩ

†CAB COMPARATOR #1

COUNT

1

DQ

LATCH

0

DQ

CLK

1 BIT 1 (LSB)

CLOCK

15

φ1 (AUTO BALANCE)

φ2 (SAMPLE UNKNOWN)

†Cascaded Auto Balance (CAB)

14

8

VAA- VSS

9 CE1

7 CE2

NOTE: CE1 and CE2 inputs and data outputs have standard CMOS protection networks to VDD and VSS. Analog inputs and clock have

standard CMOS protection networks to VAA+ and VAA-.

Timing Diagrams

DATA SHIFTED INTO

OUTPUT REGISTERS

1

CLOCK

0

1

B1 - B4, DC & OF

0

φ1

AUTO

BALANCE

tHO

φ2

SAMPLE 1

COMPARATOR DATA

LATCHED

AUTO

BALANCE

SAMPLE 2

AUTO

BALANCE

SAMPLE 3

DATA VALID 0

DATA VALID 1

DATA VALID 2

tD

FIGURE 1. TIMING DIAGRAM

CE1

CE2

BITS 1-4

DC, OF

tDIS

tEN

tDIS

HIGH

IMPEDANCE

FIGURE 2. OUTPUT ENABLE/DISABLE TIMING

tEN

HIGH

IMPEDANCE

HIGH

IMPEDANCE

4-11

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