PSB2134 데이터 시트보기 (PDF) - Infineon Technologies

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PSB2134

Two Channel Codec Filter for Terminal Applications SICOFI®2-TE

Infineon Technologies 

1.3 Pin Definition and Functions

PSB 2132

PSB 2134

Overview

Pin No. Symbol Input (I) Function

Output (O)

Common Pins for all Channels

24

VDDD

I

21

GNDD I

52

VDDA12

I

56

VREF

I/O

57

VDDREF

I

31

FSC

I

32

BCL

I

26,30 DU

I/O

27,29 DD

I/O

23

RESET I

22

DCL

I

17

CS

I

18

DCLK I

+ 5 V supply for the digital circuitry 1)

Ground Digital, not internally connected to

GNDA1,2,(3,4)

All digital signals are referred to this pin

+ 5 V Analog supply voltage for channel 1 and 2 1)

Reference voltage, has to be connected to a 220 nF

cap. to ground, can also be used as virtual ground

for analog inputs and outputs (high-ohmic buffer

needed !!!)

+ 5 V Analog supply voltage (100 nF cap. required)

Frame synchronization clock, 8 kHz, identifies the

beginning of the frame, individual time slots are

referenced to this pin, FSC must be synchronous to

DCL and BCL

IOM-2 bit clock 768 kHz, determines the rate at

which PCM data is shifted into or out of the

PCM-ports

IOM-2 Data Upstream interface. Transmits or

receives PCM data in 8 bit bursts. Both pins must be

connected together.

IOM-2 Data Downstream interface. Transmits or

receives PCM data in 8 bit bursts. Both pins must be

connected together.

Reset input - forces the device to default mode,

active low

Master clock input 1536 kHz, synchronous to FSC,

must be available if the SICOFI2/4-TE is operating

µ-Controller interface: chip select enable to read or

write data, active low

µ-Controller interface: data clock, shifts data from or

to device, the maximum clock rate is 8192 kHz

Semiconductor Group

8

09.97

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