GL800HT25 데이터 시트보기 (PDF) - GENESYS LOGIC

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GL800HT25

USB 2.0 UTMI Compliant Transceiver IP Core

GENESYS LOGIC 

GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core

5. Elasticity Buffer

Elasticity Buffer is used to compensate for difference between transmitting and receiving clocks. The USB

specification defines a maximum clock error of +/- 500 ppm. When the error is calculated over the maximum

packet size up to +/- 12 bits of drift can occur. The elasticity buffer is filled to a threshold prior to enabling the

remainder of the down stream receive logic.

Overview and underflow conditions detected in the elasticity buffer can be reported with the RXERR

signal.

6. Mux

The MUX block allows the data from the HS or FS receivers to be routed to the shared receive logic. The

state of the Mux is determined by the FSPEED input.

7. NRZI Decoder

The NRZI Decoder is compliant to standard USB 1.X specification, and it can operate at FS and HS data

rates.

8. Bit Unstuffer

The Bit Unstuffer is compliant to standard USB 1.X specification, and it can operate at FS and HS data rates.

The bit unstuffer is a state machine, which strips a stuffed 0 bit from the data stream and detects bit stuff

errors. In FS mode bit stuff errors asserts the RXERR signal. In HS mode bit stuff errors are used to

generate the EOP signal so the RXERR signal is not asserted.

9. Rx Register

Rx Register is in charge of converting serial data received from the USB to parallel data.

10. Receive State Machine

The behavior of the Receive State Machine is described at Chapter 6, Function Description.

11. NRZI Encoder

The NRZI Encoder is compliant to standard USB 1.X specification, and it can operate at FS and HS data

rates.

12. Bit Stuffer

Bit Stuffer is used by insert a zero after every six consecutive ones in the data stream before the data is NRZI

encoded in order to ensure adequate signal transitions. Bit stuffing is enabled beginning with the SYNC

Pattern and through the entire transmission. The data “one” that ends the SYNC Pattern is counted as the first

one in a sequence.

In FS mode bit stuffing by the transmitter is always enforced, without exception. If required by the bit stuffing

rules, a zero bit is inserted even after the last bit before the TXVLD signal is negated.

After 8 bits are stuffed into the USB data stream TXRDY is negated for one byte time to hold up the data

stream on the Data bus.

13. Tx Register

Tx Register is in charge of reading parallel data from the parallel application bus interface upon command

and serializing for transmission over USB.

14. Transmit State Machine

The behavior of the Transmit State Machine is described at Chapter 6, Function Description.

©2000-2003 Genesys Logic Inc.—All rights reserved.

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