GL800HT25 데이터 시트보기 (PDF) - GENESYS LOGIC

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GL800HT25

USB 2.0 UTMI Compliant Transceiver IP Core

GENESYS LOGIC 

GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core

CHAPTER 2 FEATURES

Complies with Universal Serial Bus Specification Rev. 2.0.

Complies with USB 2.0 Transceiver Macrocell Interface (UTMI) Specification.

Supports 480 Mbit/s "High Speed" (HS) / 12 Mbit/s “Full Speed” (FS), FS Only serial data transmission

rates.

16 bit Bi-directional Serial Interface Engine (SIE) bus.

SYNC/EOP generation and checking.

Supports “Chirp” for High Speed recognition.

Data and clock recovery from serial stream on the USB.

Bit-stuffing / unstuffing; Bit stuff error detection.

Holding registers to stage transmit and receive data.

Supports Reset and Suspend.

Single parallel data clock output with on-chip PLL to generate higher speed serial data clocks.

Available in 48 pin LQFP package or IP macrocell on the 0.35µm UMC / 0.25µm TSMC standard CMOS

processes.

©2000-2003 Genesys Logic Inc.—All rights reserved.

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