GL800HT25 데이터 시트보기 (PDF) - GENESYS LOGIC

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GL800HT25

USB 2.0 UTMI Compliant Transceiver IP Core

GENESYS LOGIC 

GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core

CHAPTER 3 BLOCK DIAGRAM

3.1 System Configuration

USB 2.0 Transceiver Macrocell Interface

Device

SIE

Specific

Logic

(Serial Interface

Engine)

UTMI

GL800

USB 2.0

Figure 3.1 - System Diagram

1. GL800HT25

The USB 2.0 UTMI Transceiver, which handles the low level USB protocol and signaling, and shifts the

clock domain of the data from the USB 2.0 rate to one that is compatible with the general logic.

2. Serial Interface Engine

The Serial Interface Engine can be further sub-divided into 2 types of sub-blocks; the SIE control logic and

the Endpoint logic. The SIE control logic contains the USB PID and address recognition logic, and other

sequencing and state machine logic to handle USB packets and transactions. The Endpoint logic contains

the endpoint specific logic: endpoint number recognition, FIFOs and FIFO control, etc.

SIE logic module can be developed by peripheral vendors or purchased from IP vendors. The

standardization of the UTMI allows multiple sources of SIE logic to connect with GL800HT25 to

implement the USB 2.0 High-Speed design.

3. Device Specific Logic

This block is the glue that ties the USB interface to the specific application of the device.

©2000-2003 Genesys Logic Inc.—All rights reserved.

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