GS71108ATP-12I 데이터 시트보기 (PDF) - Unspecified

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GS71108ATP-12I

128K x 8 1Mb Asynchronous SRAM

Unspecified 

Read Cycle 1: CE = OE = VIL, WE = VIH

Address

Data Out

tOH

Previous Data

tRC

tAA

Read Cycle 2: WE = VIH

Address

CE

OE

Data Out

tRC

tAA

tAC

tLZ

tOE

tOLZ

High impedance

GS71108ATP/J/SJ/U

Data valid

tHZ

tOHZ

DATA VALID

Rev: 1.04a 10/2002

6/14

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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