GS9000D 데이터 시트보기 (PDF) - Gennum -> Semtech
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GS9000D Datasheet PDF : 9 Pages
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PIN DESCRIPTIONS
PIN NO.
SYMBOL
15
SWC
16
PCLK
17
PD0
18
19-25
VDD
PD1 - PD7
26
VSS
27
PD8
28
PD9
TYPE
DESCRIPTION
Input
Sync Warning Control. Analog input used to set the HSYNC Error Rate (HER). This is
accomplished by an external RC time constant connected to this pin.
Output Parallel Clock Output. CMOS (TTL compatible) clock output where the rising edge of the
clock is located at the centre of the parallel data window within a given tolerance. See Fig. 7.
Output Parallel Data Output - Bit 0 (LSB). CMOS (TTL compatible) descrambled parallel data output
from the serial to parallel convertor representing the least significant bit (LSB).
Power Supply. Most positive power supply connection.
Outputs Parallel Data Outputs - Bit 1 to Bit 7. CMOS (TTL compatible) descrambled parallel data
outputs from the serial to parallel convertor representing data bit 1 through data bit 7.
Power Supply. Most negative power supply connection.
Output Parallel Data Output. CMOS (TTL compatible) descrambled parallel data output from the
serial to parallel convertor representing data bit 8.
Output Parallel Data Output - Bit 9 (MSB). CMOS (TTL compatible) descrambled data output from
the serial to parallel convertor representing the most significant bit (MSB).
INPUT/OUTPUT CIRCUITS
VDD
VDD
SSC
REXT
VDD
SDI
SCI
EXTERNAL
COMPONENTS
Fig. 2 Pin 11 SSC
VDD
BIAS
SDI
SCI
VDD
VDD
Fig. 4 Pins 5 - 8 SDI - SCI
SCE
Fig. 3 Pin 14 SCE
GENNUM CORPORATION
5 of 9
18784 - 3
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