GS9001 데이터 시트보기 (PDF) - Gennum -> Semtech

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GS9001

EDH Coprocessor

Gennum -> Semtech 

GS9001 - DETAILED DEVICE DESCRIPTION.

The GS9001 contains all functional blocks required to implement The presence of ancillary data is indicated by a logic high that

Error Detection and Handling according to SMPTE RP165. It extends from the Data ID word to the Checksum word of each

also provides Field, Vertical, and Horizontal timing information ancillary packet. These timing signals are available on

as well as Ancillary Data and TRS-ID indication. The device

offers standard independent operation and an I2C serial

communications interface to allow reading/writing of error

dedicated output pins and through the I2C communications

interface.

flags, device configuration and video standards format. The The control logic also verifies incoming data validity by checking

device can also be operated in stand alone mode without the the occurrence of consecutive TRS-IDs. If the absence of

I2C interface with error flags available on dedicated output seven consecutive TRS-IDs is detected, a “NO TRS” flag is

pins. In all modes, the device latency is four clock cycles.

Automatic Standards Detection

D This block analyses the incoming 8 or 10 bit data to determine

whether it is component or composite. In total, six standards

E are automatically detected. For composite data conforming to

SMPTE 259M, the Timing Reference Signal and Identification

D (TRS-ID) packet contains line and field information used to

detect the format. For component data conforming to SMPTE

N S 125M, the TRS-ID packets for End of Active Video (EAV)and

Start of Active Video (SAV) are used to determine the format.

E N The TRS information is then used to determine whether the

composite signal is NTSC or PAL, or whether the component

M IG signal has 13.5 MHz or 18 MHz luminance samples.

Noise immunity has also been included, to ensure that

M S momentary signal interruption does not affect the auto-

standards detection function. This built in noise immunity

O E results in delayed switching time between standards. Delays

range from as little as eight lines when switching between

C D componentstandardstoasmuchasfourframeswhenswitching

between PAL and NTSC composite standards. The latter

E delay is due to the method used to differentiate PAL and NTSC,

R W which counts the number of lines per frame and requires four

sequential frames before switching standards. Manual override

E of the auto-standard feature is provided via the I2C interface,

for applications where the standards recognition delay is

T N intolerable. Standards indication is provided on multiplexed

output pins or via the I2C interface.

NO R ControlLogic

The control logic coordinates operation and extracts timing

O signals such as vertical blanking, horizontal sync, field ID,

F ancillary data indication and TRS-ID indication.

output on pin 34. This flag is reset once seven consecutive

TRS-IDs occur.

CRC Calculation

A cyclic redundancy check (CRC) is calculated for each video

field according to the CRC-CCITT polynomial X16+X12+X5+1.

Separate CRCs are calculated for active picture and full field

to provide an indication that active video is still intact despite

possible full field errors. This allows the user to distinguish

between different classes of data errors, which yields the best

compromise in error detection for all types of equipment. In

order to provide compatibility between 8 bit and 10 bit systems,

all data words with values between 3FCH and 3FFH inclusive,

are recoded as 3FFH at the input of the polynomial generator.

Start and end points for the CRC calculation are as defined in

RP165 and depend on the standard and check field being

calculated. Calculated CRC words can be read through the

I2C interface.

CRC Comparison

The GS9001 can be configured for transmit or receive mode.

In receive mode, the calculated CRC is checked against the

incoming CRC embedded in the error data packet. Any

mismatch will generate status error flags to indicate transmission

related error flags in either active picture, full field or both. The

error flags resulting from CRC mismatch are full field error

detected here (EDH) and active picture EDH.

Ancillary Checksum Verification

The ancillary data checksums are also verified to ensure data

integrity. Ancillary data is preceded by the Data Header, Data

ID, Block Number and Data Count. The Data Count shows the

number of ancillary words contained in each ancillary data

The vertical blanking interval signal is active during the digital

vertical blanking period for all signal formats. The horizontal

sync signal is provided as a pulse with a duration of one clock

period for every TRS-ID occurrence in composite video. For

component video, the horizontal sync is a positive going pulse

packet. A checksum is calculated for each incoming ancillary

data packet and compared with the transmitted checksum.

Any difference is reported as an error via the ancillary EDH

error flag. A separate ANC EXT error flag is also provided to

indicate corruption of the EDH data packet.

which starts at EAV and ends at SAV. Three field ID bits (pins Error Flags and Formatting

40, 41, 42) indicate the two fields for component video standards,

the four colour fields for composite NTSC or eight colour fields

for composite PAL.

The ancillary data indication allows external circuitry to identify

ancillary data in the data stream for extraction or masking.

This block performs the functions of error flag reporting and

recoding, EDH data packet construction, programmable

interrupt generation and interface with the I2C communication

block.

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