GS9091B 데이터 시트보기 (PDF) - Gennum -> Semtech

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GS9091B

GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI

Gennum -> Semtech 

Table 1-1: Ball List and Description (Continued)

Ball

Name

K6

SDIN_TDI

K7, K8, J8, J9 STAT[0:3]

K9

RD_CLK

Timing

Type Description

Synchronous

with

SCLK_TCK

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS / LVTTL compatible.

Serial Data Input / Test Data Input

Host Mode (JTAG_EN = LOW):

SDIN_TDI operates as the host interface serial input, SDIN, used to

write address and configuration information to the internal

registers of the device.

JTAG Test Mode (JTAG_EN = HIGH):

SDIN_TDI operates as the JTAG test data input, TDI.

Synchronous

with PCLK or

RD_CLK

Output

MULTI FUNCTION I/O PORT

Signal levels are LVCMOS / LVTTL compatible.

Programmable multi-function outputs. By programming the bits is

the IO_CONFIG register, each pin can output one of the following

signals:

•H

•V

•F

• FIFO_LD

• ANC

• EDH_DETECT

• FIFO_FULL

• FIFO_EMPTY

These pins are set to certain default values depending on the

configuration of the device and the internal FIFO mode selected.

See Section 3.12 for details.

–

Input FIFO READ CLOCK

Signal levels are LVCMOS / LVTTL compatible.

The application layer clocks the parallel data out of the FIFO on the

rising edge of RD_CLK.

GS9091B GenLINX® II 270Mb/s Deserializer for SDI

and DVB-ASI

Data Sheet

38910 - 2

July 2008

11 of 71

Proprietary & Confidential

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