HD49340HNP 데이터 시트보기 (PDF) - Renesas Electronics

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HD49340HNP

CDS/PGA & 10-bit A/D Converter

Renesas Electronics 

HD49340NP/HNP

Detailed Timing Specifications at Pre-Blanking

Figure 5 shows the pre-blanking detailed timing specifications.

PBLK

Vth

Digital output ADC

(D0 to D9) data

Clamp level

VOH

ADC

data

tPBLK

ADCLK × 2 clocks

VOL

ADCLK × 10 clocks

(shifts one clock cycle depending

on the PBLK input timing)

When serial data SPinv bit is set to low

(When the SPinv is set to high, the PBLK polarity is inverted.)

Figure 5 Detailed Timing Specifications at Pre-Blanking

Detailed Timing Specifications when ADCIN Input Mode is Used

Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.

ADCIN

(2)

ADCLK

D0 to D9

(1)

(3)

(4)

(5)

Vth

VDD/2

Figure 6 Detailed Timing Chart when ADCIN Input Mode is Used

Table 9 Timing Specifications when ADCIN Input Mode is Used

No.

(1)

(2), (3)

(4)

(5)

Timing

Signal fetch time

ADCLK tWH min./tWL min.

ADCLK rising to digital output hold time

ADCLK rising to digital output delay time

Symbol

tADC1

tADC2, 3

tAHLD4

tAOD5

Min

—

Typ × 0.85

10

—

Typ

(6)

1/2fADCLK

14.5

23.5

Max

—

Typ × 1.15

—

31.5

Unit

ns

ns

ns

ns

Rev.1.0 Apr 20, 2004 page 11 of 21

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