HEF4021B 데이터 시트보기 (PDF) - NXP Semiconductors.
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HEF4021B Datasheet PDF : 14 Pages
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NXP Semiconductors
HEF4021B
8-bit static shift register
Table 7. Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Extrapolation formula
tPLH
LOW to HIGH
CP to Qn
propagation delay see Figure 4
5V
10 V
[1] 88 ns + (0.55 ns/pF) CL
39 ns + (0.23 ns/pF) CL
15 V
32 ns + (0.16 ns/pF) CL
PL to Qn
see Figure 4
5V
10 V
78 ns + (0.55 ns/pF) CL
39 ns + (0.23 ns/pF) CL
15 V
32 ns + (0.16 ns/pF) CL
tt
transition time
Qn; see Figure 4 5 V [1] 10 ns + (1.00 ns/pF) CL
10 V
9 ns + (0.42 ns/pF) CL
15 V
6 ns + (0.28 ns/pF) CL
tsu
set-up time
DS to CP;
see Figure 5
5V
10 V
15 V
Dn to PL;
see Figure 6
5V
10 V
15 V
th
hold time
DS to CP;
see Figure 5
5V
10 V
15 V
Dn to PL;
see Figure 6
5V
10 V
15 V
tW
pulse width
CP = LOW;
minimum width;
see Figure 5
5V
10 V
15 V
PL = HIGH;
minimum width;
see Figure 6
5V
10 V
15 V
trec
recovery time
PL input;
5V
see Figure 6
10 V
15 V
fclk(max)
maximum clock
frequency
CP input;
see Figure 5
5V
10 V
15 V
Min Typ Max Unit
-
115 230 ns
-
50 100 ns
-
40 80 ns
-
105 210 ns
-
50 100 ns
-
40 80 ns
-
60 120 ns
-
30 60 ns
-
20 40 ns
+25 −15 -
ns
+25 −10 -
ns
+15 −5 -
ns
50 25 -
ns
30 10 -
ns
20
5-
ns
40 20 -
ns
20 10 -
ns
15
8-
ns
+15 −10 -
ns
15
0-
ns
15
0-
ns
70 35 -
ns
30 15 -
ns
24 12 -
ns
70 35 -
ns
30 15 -
ns
24 12 -
ns
50 10 -
ns
40
5-
ns
35
5-
ns
6 13 -
MHz
15 30 -
MHz
20 40 -
MHz
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
HEF4021B_4
Product data sheet
Rev. 04 — 10 November 2008
© NXP B.V. 2008. All rights reserved.
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