HEF4505B 데이터 시트보기 (PDF) - Philips Electronics

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HEF4505B

64-bit, 1-bit per word random access read/write memory

Philips Electronics 

Philips Semiconductors

64-bit, 1-bit per word random access

read/write memory

Product specification

HEF4505B

LSI

DESCRIPTION

The HEF4505B is a 64-bit, 1-bit per word, fully decoded

and completely static, random access memory. The

memory is strobed for reading or writing only when the

strobe input (ST), chip enable inputs (CE1 and CE2) are

HIGH simultaneously. The output data is available at the

data output (DOUT) only when the memory is strobed, the

read/write input (R/W) is HIGH and after the read access

time has passed. Note that the three-state output is initially

disabled and always goes to the LOW state before data is

valid. The output is disabled in the high-impedance

OFF-state, when the memory is not strobed or R/W is

LOW. R/W may remain HIGH during a read cycle or LOW

during a write cycle. The output data has the same polarity

as the input data.

Fig.1 Pinning diagram.

HEF4505BP(N): 14-lead DIL; plastic

(SOT27-1)

HEF4505BD(F): 14-lead DIL; ceramic (cerdip)

(SOT73)

( ): Package Designator North America

PINNING

A0 to A5

CE1, CE2

R/W

ST

DIN

DOUT

address inputs

chip enable inputs

read/write input

strobe input

data input

data output

FUNCTION TABLE

ST, CE1, CE2 R/W

DOUT

L

LZ

H

LZ

L

HZ

H

H equal to memory data

MODE

disabled

write

disabled

read

Note

1. H = HIGH state (the more positive voltage)

L = LOW state (the less positive voltage)

Z = high-impedance OFF-state

SUPPLY VOLTAGE

RATING

−0,5 to +15

OPERATING

4,5 to 15 V

Note

1. Minimum standby voltage for data retention is 3 V.

FAMILY DATA, IDD LIMITS category LSI

See Family Specifications

January 1995

2

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