HEC4751VT 데이터 시트보기 (PDF) - Philips Electronics
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HEC4751VT Datasheet PDF : 10 Pages
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Philips Semiconductors
Universal divider
Product specification
HEF4751V
LSI
Fig.4 Timing diagram showing programme data inputs.
Allocation of data input
FETCH
INPUTS
PERIOD A3 A2 A1 A0 B3 B2 B1 B0 SI
0
n0A
n0B
bin
1
n1A
n1B
X
2
n2A
n2B
X
3
n3A
n3B
X
4
n4A
n4B
X
5
n5A
n5B
X
6
M
C0b
control
1⁄2
channel
control
X
Allocation of data input B3 to B0 during fetch period 6
B3
B2
L
L
L
H
H
L
H
H
C0b DIVISION RATIO
1
2
5
10/11
B1
B0
1⁄2 CHANNEL CONFIGURATION
L
L
H=1
L
H
H
H
H
L
H = 2; nh = 0
H = 2; nh = 1
test state
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
January 1995
5
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