HI-3282CLT 데이터 시트보기 (PDF) - Holt Integrated Circuits
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HI-3282CLT Datasheet PDF : 14 Pages
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HI-3282, HI-3282B
AC ELECTRICAL CHARACTERISTICS
Vcc = 5V, GND = 0V, TA = Operating Temperature Range and fclk = 1mhz +0.1% with 60/40 duty cycle
PARAMETER
SYMBOL
LIMITS
MIN
TYP
CONTROL WORD TIMING
Pulse Width - CWSTR
tCWSTR
50
Setup - DATA BUS Valid to CWSTR HIGH
tCWSET
50
Hold - CWSTR HIGH to DATA BUS Hi-Z
tCWHLD
0
RECEIVER TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
tD/R
Low Speed
tD/R
Delay - D/R LOW to EN L0W
tD/REN
0
Delay - EN LOW to D/R HIGH
tEND/R
Setup - SEL to EN L0W
tSELEN
10
Hold - SEL to EN HIGH
tENSEL
10
Delay - EN L0W to DATA BUS Valid
tENDATA
50
Delay - EN HIGH to DATA BUS Hi-Z
tDATAEN
Pulse Width - EN1 or EN2
tEN
80
Spacing - EN HIGH to next EN L0W
tENEN
50
FIFO TIMING
Pulse Width - PL1 or PL2
tPL
50
Setup - DATA BUS Valid to PL HIGH
tDWSET
50
Hold - PL HIGH to DATA BUS Hi-Z
tDWHLD
10
Spacing - PL1 or PL2
tPL12
0
Delay - PL2 HIGH to TX/R LOW
tTX/R
TRANSMISSION TIMING
Spacing - PL2 HIGH to ENTX HIGH
tPL2EN
0
Delay - ENTX HIGH to 429DO or 429D0: High Speed
Delay - ENTX HIGH to 429DO or 429D0: Low Speed
Delay - 32nd ARINC Bit to TX/R HIGH
tENDAT
tENDAT
tDTX/R
Spacing - TX/R HIGH to ENTX L0W
tENTX/R
0
REPEATER OPERATION TIMING
Delay - EN LOW to PL LOW
tENPL
0
Hold - PL HIGH to EN HIGH
tPLEN
0
Delay - TX/R LOW to ENTX HIGH
tTX/REN
0
Master Reset Pulse Width
tMR
50
ARINC Data Rate and Bit Timing
UNITS
MAX
ns
ns
ns
16
µs
128
µs
ns
200
ns
ns
ns
80
ns
30
ns
ns
ns
ns
ns
ns
ns
840
ns
µs
25
µs
200
µs
50
ns
ns
ns
ns
ns
ns
± 1%
HOLT INTEGRATED CIRCUITS
9
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