HI2301 데이터 시트보기 (PDF) - Intersil
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HI2301 Datasheet PDF : 13 Pages
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HI2301
Application Circuits (Continued)
ACO4
+4.75V
20K
0.1µ
0.1µ
+3.3V (DIGITAL)
CLOCK IN
CK
0.1µ
CLAMP PULSE IN
Q
LATCH
(NOTE 5)
24 23 22 21 20 19 18 17
+4.75V (ANALOG)
25
16
D0
VIDEO IN
(NOTE 6)
10µ 75
26
0.1µ
27
28
29
15
D1
14
D2
13
D3
12
D4
10p
30
11
D5
31
10
D6
32
9
D7
0.01µ
12345678
GND (ANALOG) GND (DIGITAL)
NOTES:
5. Although the ADC sampling clock latches the clamp pulse, it is not needed for basic clamp operation. However, depending on the
relationship between the sampling frequency and the clamp pulse frequency, a small abeat might be generated as VSAG. The latch circuit
is valid at this time.
6. Take care that the phase of ADIN input is inverted against the phase of the digital output, because the use of the built-in inverting amplifier
is standard. (Refer to “Digital Output”.)
FIGURE 4. CLAMP USAGE EXAMPLE WHEN NOT USING THE INTERNAL AMPLIFIER
4-10
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