HI5702 데이터 시트보기 (PDF) - Intersil

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HI5702

10-Bit, 40 MSPS A/D Converter

Intersil 

HI5702

PIN #

TABLE 1. PIN DESCRIPTIONS

NAME

DESCRIPTION

phase, the VIN pins see only the on-resistance of a switch

and CS. The small values of these components result in a

typical full power bandwidth of 250MHz.

1

DVCC

Digital Supply.

2

DGND

Digital Ground.

3

DVCC

Digital Supply.

4

DGND

Digital Ground.

5

AVCC

Analog Supply.

6

AGND

Analog Ground.

7

VREF+

Positive Reference.

8

VREF -

Negative Reference.

9

VIN+

Positive Analog Input.

10

VIN-

Negative Analog Input.

11

VCM

DC Output Voltage Source.

12

AGND

Analog Ground.

13

AVCC

Analog Supply.

14

AGND

Analog Ground.

15

DFS

Data Format Select.

16

D9

Data Bit 9 Output (MSB).

17

D8

Data Bit 8 Output.

18

D7

Data Bit 7 Output.

19

D6

Data Bit 6 Output.

20

D5

Data Bit 5 Output.

21

DGND

Digital Ground.

22

CLK

Input Clock.

23

DVCC

Digital Supply.

24

D4

Data Bit 4 Output.

25

D3

Data Bit 3 Output.

26

D2

Data Bit 2 Output.

27

D1

Data Bit 1 Output.

28

D0

Data Bit 0 Output (LSB).

Detailed Description

Theory of Operation

The HI5702 is a 10-bit fully differential sampling pipeline A/D

converter with digital error correction. Figure 13 depicts the

circuit for the front end differential-in-differential-out sample-

and-hold (S/H). The switches are controlled by an internal

clock which is a non-overlapping two phase signal, φ1 and

φ2, derived from the master clock. During the sampling

phase, φ1, the input signal is applied to the sampling capaci-

tors, CS. At the same time the holding capacitors, CH, are

discharged to analog ground. At the falling edge of φ1 the

input signal is sampled on the bottom plates of the sampling

capacitors. In the next clock phase, φ2, the two bottom

plates of the sampling capacitors are connected together

and the holding capacitors are switched to the op-amp out-

put nodes. The charge then redistributes between CS and

CH completing one sample-and-hold cycle. The output is a

fully-differential, sampled-data representation of the analog

input. The circuit not only performs the sample-and-hold

function but will also convert a single-ended input to a fully-

differential output for the converter core. During the sampling

φ1

VIN +

CS

φ1 CH

φ2

-+

+-

VIN -

φ1

CS

φ1

CH

φ1

VOUT +

VOUT -

φ1

FIGURE 21. ANALOG INPUT SAMPLE-AND-HOLD

As illustrated in the Functional Block Diagram and the Tim-

ing Diagram in Figure 1, nine identical pipeline subconverter

stages, each containing a two-bit flash and a two-bit multiply-

ing digital-to-analog converter, follow the S/H circuit with the

tenth stage being a one bit flash converter. Each converter

stage in the pipeline will be sampling in one phase and

amplifying in the other clock phase. Each individual sub-con-

verter clock signal is offset by 180 degrees from the previous

stage clock signal with the result that alternate stages in the

pipeline will perform the same operation.

The two-bit digital output of each stage is fed to a digital delay

line controlled by the internal clock. The purpose of the delay

line is to align the digital output data to the corresponding

sampled analog input signal. This delayed data is fed to the

digital error correction circuit which corrects the error in the

output data with the information contained in the redundant

bits to form the final 10-bit output for the converter.

Because of the pipeline nature of this converter, the data on

the bus is output at the 7th cycle of the clock after the analog

sample is taken. This delay is specified as the data latency.

After the data latency time, the data representing each suc-

ceeding sample is output at the following clock pulse. The

output data is synchronized to the external clock by a double

buffered latching technique.

The output of the digital correction circuit is available in two’s

complement or binary format depending on the condition of

the Data Format Select (DFS) input.

Analog Input, Differential Connection

The analog input to the HI5702 is a differential input that can

be configured in various ways depending on the signal

source and the required level of performance. A fully differ-

ential connection (Figure 15) will give the best performance

for the converter.

VIN+

VIN+

R

HI5702

VCM

VIN-

R

VIN-

FIGURE 22. AC COUPLED DIFFERENTIAL INPUT

4-1512

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