HI5702 데이터 시트보기 (PDF) - Intersil
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HI5702 Datasheet PDF : 14 Pages
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HI5702
Since the HI5702 is powered by a single +5V analog supply,
the analog input is limited to be between ground and +5V,
which implies the common mode voltage can range of 0.625V
to 4.375V. The performance of the ADC does not change sig-
nificantly with the value of the common mode voltage.
A DC voltage source, VCM, about half way between the top
and bottom reference voltages, is made available to the user
to help simplify circuit design when using a differential input.
This low output impedance voltage source is not designed to
be a reference but makes an excellent bias source and stays
within the common mode range over temperature. It has a
temperature coefficient of about 200ppm.
Assume the difference between VREF+, typically 3.25V, and
VREF-, typically 2V, is 1.25V in Figure 15. Fullscale is
achieved when VIN+ and VIN- inputs are 1.25VP-P, with VIN-
being 180 degrees out of phase with VIN+. The converter will
be at positive fullscale when the VIN+ input is at VCM +
0.625V and VIN- is at VCM - 0.625V (VIN+ - VIN- = 1.25V).
Conversely, the ADC will be at negative fullscale when the
VIN+ input is equal to VCM - 0.625V and VIN- is at VCM +
0.625V (VIN+ - VIN- = -1.25V).
The analog input can be DC coupled as long as the inputs
are within the common mode range, Figure 16.
VIN+
VIN+
R
C
HI5702
VCM
R
VIN-
VIN-
FIGURE 23. DC COUPLED DIFFERENTIAL INPUT
The resistors, R, in Figure 16 are not absolutely necessary
but will improve performance. Values of 100Ω or less are
typical. A capacitor, C, connected from VIN+ to VIN- will help
common mode any noise on the inputs, also improving per-
formance. Values around 20pF are sufficient and can be
used on AC coupled inputs as well.
Analog Input, Single-Ended Connection
The configuration shown in Figure 17 may be used with a
single ended AC coupled input.
VIN
VIN+
sinewave riding on a positive voltage equal to VDC, the con-
verter will be at positive fullscale when VIN+ is at VDC +
1.25V and will be at negative fullscale when VIN is equal to
VDC - 1.25V. In this case, VDC could range between 1.25V
and 3.75V without a significant change in ADC performance.
The simplest way to produce VDC is to use the VCM output
of the HI5702.
The analog input can be DC coupled as long as the input is
within the common mode range, Figure 18.
VIN
VDC
VIN+
R
C
HI5702
VIN-
FIGURE 25. DC COUPLED SINGLE ENDED INPUT
The resistor, R, in Figure 18 is not absolutely necessary but
will improve performance. Values of 100Ω or less are typical.
A capacitor, C, connected from VIN+ to VIN- will help com-
mon mode any noise on the inputs, also improving perfor-
mance. Values around 20pF are sufficient and can be used
on AC coupled inputs as well.
A single ended source may give better overall system perfor-
mance if it is first converted to differential before driving the
HI5702. Also refer to the application note AN9413, “Driving
the Analog Input of the HI5702”. This application note
describes several different ways of driving the analog differ-
ential inputs.
Reference Input, VREF- VREF+
The converter requires two reference voltages connected to
the VREF pins. The voltage range of the part with a differential
input will be VREF+ - VREF-. The HI5702 is tested with VREF-
equal to 2V and VREF+ equal to 3.25V for an input range of
1.25V. VREF+ and VREF- can differ from the above voltages
as long as the common mode voltage between the reference
pins ((VREF+ + VREF-) / 2) does not exceed 2.65V ±50mV
and the limits on VREF+ and VREF- are not exceeded.
In order to minimize overall converter noise it is recommended
that adequate high frequency decoupling be provided at the
reference input pin.
R
VDC
HI5702
Digital Control and Clock Requirements
The HI5702 provides a standard high-speed interface to
external TTL logic families.
VIN-
FIGURE 24. AC COUPLED SINGLE ENDED INPUT
In order to ensure rated performance of the HI5702, the duty
cycle of the clock should be held at 50%. It must also have
low jitter and operate at standard TTL levels.
Sufficient headroom must be provided such that the input
voltage never goes above +5V or below AGND.
Again, assume the difference between VREF+, typically
3.25V, and VREF-, typically 2V, is 1.25V. If VIN is a 2.5VP-P
A Data Format Select (DFS) pin is provided which will deter-
mine the format of the digital data. When at logic low the
data will be output in offset binary format. When at a logic
high the data will be output in a two’s complement format.
Refer to Table 2 for further information.
4-1513
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