HI5731 데이터 시트보기 (PDF) - Intersil

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HI5731

12-Bit, 100MSPS,High Speed D/A Converter

Intersil 

HI5731

Absolute Maximum Ratings

Digital Supply Voltage VCC to DGND . . . . . . . . . . . . . . . . . . . +5.5V

Negative Digital Supply Voltage DVEE to DGND . . . . . . . . . . -5.5V

Negative Analog Supply Voltage AVEE to AGND, ARTN . . . . . -5.5V

Digital Input Voltages (D11-D0, CLK) to DGND. . . . . DVCC to -0.5V

Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . ±2.5mA

Voltage from CTRL IN to AVEE . . . . . . . . . . . . . . . . . . . . 2.5V to 0V

Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . ±2.5mA

Reference Input Voltage Range . . . . . . . . . . . . . . . . . .-3.7V to AVEE

Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

Thermal Information

Thermal Resistance (Typical, Note 1)

θJA (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

50

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

70

Maximum Junction Temperature

HI5731BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications AVEE, DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal

TA = 25oC for All Typical Values

PARAMETER

SYSTEM PERFORMANCE

Resolution

Integral Linearity Error, INL

Differential Linearity Error, DNL

Offset Error, IOS

Full Scale Gain Error, FSE

Full Scale Gain Drift

TEST CONDITIONS

(Note 4) (“Best Fit” Straight Line)

(Note 4)

(Note 4)

(Notes 2, 4)

With Internal Reference

HI5731BI

TA = -40oC TO 85oC

MIN TYP MAX

12

-

-

-

0.75 1.5

-

0.5

1.0

-

20

75

-

1

10

-

±150

-

Offset Drift Coefficient

Full Scale Output Current, IFS

Output Voltage Compliance Range

DYNAMIC CHARACTERISTICS

Throughput Rate

Output Voltage Full Scale Step

Settling Time, tSETT, Full Scale

Singlet Glitch Area, GE (Peak)

Doublet Glitch Area, (Net)

Output Slew Rate

Output Rise Time

Output Fall Time

Spurious Free Dynamic Range within a Window

(Note 3)

(Note 3)

(Note 3)

(Note 3)

To ±0.5 LSB Error Band RL = 50Ω

(Note 3)

RL = 50Ω (Note 3)

RL = 50Ω, DAC Operating in Latched Mode (Note 3)

RL = 50Ω, DAC Operating in Latched Mode (Note 3)

RL = 50Ω, DAC Operating in Latched Mode (Note 3)

fCLK = 10MSPS, fOUT = 1.23MHz, 2MHz Span

fCLK = 20MSPS, fOUT = 5.055MHz, 2MHz Span

fCLK = 40MSPS, fOUT = 16MHz, 10MHz Span

fCLK = 50MSPS, fOUT = 10.1MHz, 2MHz Span

fCLK = 80MSPS, fOUT = 5.1MHz, 2MHz Span

fCLK = 100MSPS, fOUT = 10.1MHz, 2MHz Span

-

-

0.05

-

20.48

-

-1.25

-

0

100

-

-

-

20

-

-

5

-

-

3

-

-

1,000

-

-

675

-

-

470

-

-

85

-

-

77

-

-

75

-

-

80

-

-

78

-

-

79

-

UNITS

Bits

LSB

LSB

µA

%

ppm

FSR/oC

µA/oC

mA

V

MSPS

ns

pV-s

pV-s

V/µs

ps

ps

dBc

dBc

dBc

dBc

dBc

dBc

3

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