HIP5060 데이터 시트보기 (PDF) - Intersil

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HIP5060

Power Control IC Single Chip PowerSupply

Intersil 

HIP5060

Pin Descriptions

PAD NUMBER

1

2

3

4

5

6

7

8

9

10

11

12

13 & 14

15, 16, 19, 20,

23, 24, 27, 28

17, 18, 21, 22,

25, 26, 29, 30

31

32

33

34

35

36

37

DESIGNATION

AGND

VINP

SFST

IRFO

IRFI

DGD2

VDDD

VDDA

V+

SLCT

CKIO

DGD1

VDDP

S

DESCRIPTION

Analog ground.

Internal 5.1V reference.

Controls the rate of rise of the output voltage. Time is determined by an internal 0.7µA current

source and an external capacitor.

A resistor placed between this pad and IRFI converts the VCMP signal to a current for the current

sense comparator. The maximum current is set by the value of the resistor, according to the

equation: IPEAK = 32/R. Where R is the value of the external resistor in KΩ and must be greater

than 1.5KΩ but less than 10KΩ. For example, if the resistor chosen is 1.8K, the peak current will

be 17.8A. This assumes VCMP is 7.3V. Maximum output current should be kept below 20A.

See IRFO

Ground of the DMOS gate driver. This pad is used for bypassing.

Voltage input for the chip’s digital circuits. This pad also allows decoupling of this supply.

This is the analog supply and internal 12V regulator output.

This is the main supply voltage input pad to the regulator IC. Because of the high peak currents

this pad must be well bypassed with at least a 0.7µF capacitor and may be composed of seven,

single 0.1µF chip capacitors.

This pad provides for the option of using either internal 1MHz operation of for an external clock.

Floating or grounding this pad will place the internal clock at the CKIO pad. Returning this termi-

nal to VDDD or 12V will allow application of an external clock to the IC via the CKIO pad. There

is an internal 50K pull down

Clock output when SLCT is floated or grounded. External clock input when SLCT is returned to

12V.

This pad is the return for the digital supply.

These pads are used to decouple the high current pulses to the output driver transistors. The

capacitor should be at least a 0.1µF chip capacitor placed close to this pad and the DMOS

source pads.

Source pads of the DMOS power transistor.

D

Drain pads of the DMOS power transistor.

TMON

PSEN

SHRT

PSOK

VCMP

VREG

FLTN

This is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By

returning this pad to 12V the function is disabled. Returning this pad to ground will put the IC into

the thermal shutdown state. Normally, this pad is left floating. Thermal shutdown occurs at a

nominal junction temperature of +125oC.

This terminal is provided to activate the converter. This terminal may be left open or returned to

5V for normal operation. When the input is low, the DMOS driver is disabled.

25µA is internally applied to this node when there is an over-current condition.

This pad provides a delayed positive indication when the supply is enabled.

Output of the transconductance amplifier. This node is used for both gain and frequency com-

pensation of the loop.

Input to the transconductance error amplifier is available on this pad. The other input is internally

connected to the 5.1V reference, VINP, Pad 2.

This is an open drain output that remains low when V+ is too low for proper operation. This node

and PSEN are useful in multiple converter configurations. This pad will be latched low when over-

temperature, over-voltage or over-current is experienced.

5

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