HM-6518/883 데이터 시트보기 (PDF) - Intersil
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HM-6518/883 Datasheet PDF : 9 Pages
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HM-6518/883
TABLE 2. HM-6518/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
Chip Enable
Access Time
(1) TELQV VCC = 4.5 and
5.5V
Address Access
Time
(2) TAVQV VCC = 4.5 and
5.5V, Note 3
Chip Select
Output Enable
Time
(3) TSLQX VCC = 4.5 and
5.5V
Write Enable
Output Disable
Time
(4) TWLQZ VCC = 4.5 and
5.5V
Chip Select
Output Disable
Time
(5) TSHQZ VCC = 4.5 and
5.5V
Chip Enable Pulse (6) TELEH VCC = 4.5 and
Negative Width
5.5V
Chip Enable Pulse (7) TEHEL VCC = 4.5 and
Positive Width
5.5V
Address Setup
Time
(8) TAVEL VCC = 4.5 and
5.5V
Address Hold Time (9) TELAX VCC = 4.5 and
5.5V
Data Setup Time
(10) TDVWH VCC = 4.5 and
5.5V
Data Hold Time
(11) TWHDX VCC = 4.5 and
5.5V
Chip Select Write (12) TWLSH VCC = 4.5 and
Pulse Setup Time
5.5V
Chip Enable Write (13) TWLEH VCC = 4.5 and
Pulse Setup Time
5.5V
Chip Select Write
Pulse Hold Time
(14) TSLWH VCC = 4.5 and
5.5V
Chip Enable Write (15) TELWH VCC = 4.5 and
Pulse Hold Time
5.5V
Write Enable Pulse (16) TWLWH VCC = 4.5 and
Width
5.5V
Read or Write
Cycle Time
(17) TELEL VCC = 4.5 and
5.5V
GROUP A
SUB-
GROUPS
TEMPERATURE
9, 10, 11 -55oC ≤ TA ≤ +125oC
LIMITS
HM-6518B/883 HM-6518/883
MIN MAX MIN MAX
-
180
-
250
UNITS
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC
-
180
-
250
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC
5
-
5
-
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC
-
120
-
160
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC
-
120
-
160
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC 180
-
250
-
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC 100
-
100
-
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC
0
-
0
-
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC 40
-
50
-
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC 80
-
110
-
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC
0
-
0
-
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC 100
-
130
-
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC 100
-
130
-
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC 100
-
130
-
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC 100
-
130
-
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC 100
-
130
-
ns
9, 10, 11 -55oC ≤ TA ≤ +125oC 280
-
350
-
ns
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC -2.0V; input rise and fall times: 5ns (max); input and output timing reference level: 1.5V; output load:
-1TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
6-88
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