HM-6518883 데이터 시트보기 (PDF) - Intersil
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HM-6518883 Datasheet PDF : 9 Pages
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HM-6518/883
TRUTH TABLE
TIME
REFERENCE
E
INPUTS
S1
W
A
OUTPUTS
D
Q
FUNCTION
-1
H
H
X
X
X
Z
Memory Disabled
0
X
H
V
X
Z
Cycle Begins, Addresses are Latched
1
L
L
H
X
X
X
Output Enabled
2
L
L
H
X
X
V
Output Valid
3
L
H
X
X
V
Output Latched
4
H
H
X
X
X
Z
Device Disabled, Prepare for Next Cycle
(Same as -1)
5
X
H
V
X
Z
Cycle Ends, Next Cycle Begins
(Same as 0)
NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.
In the HM-6518/883 read cycle the address information is
latched into the on chip registers on the falling edge of E
(T = 0). Minimum address setup and hold time require-
ments must be met. After the required hold time the
addresses may change state without affecting device oper-
ation. In order for the output to be read S1, S2 and E must
be low, W must be high. When E goes high the output data
is latched into an on chip register. Taking either or both S1
or S2 high, forces the output buffer to a high impedance
state. The output data may be re-enabled at any time by
taking S1 and S2 low. On the falling edge of E the data will
be unlatched.
Timing Waveforms
(8) TAVEL
A
TEHEL (7)
(9)
TELAX
VALID
TELEL (17)
TELEH (6)
(8) TAVEL
TEHEL (7)
NEXT
E
W
D
Q
S1,
S2
TIME
REFERENCE
HIGH Z
-1
TWLEH (13)
TELWH (15)
TWLWH (16)
TDVWH (10)
VALID DATA
TSLWH (14)
TWLSH (12)
TWHDX (11)
0
1
FIGURE 2. WRITE CYCLE
23
4
5
6-90
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