HM6264BLPI 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics
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HM6264BLPI Datasheet PDF : 17 Pages
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HM6264BI Series
Write Cycle
HM6264BI-10 HM6264BI-12
Parameter
Symbol Min Max Min Max Unit Notes
Write cycle time
t WC
100 — 120 — ns
Chip selection to end of write
t CW
80
—
85
—
ns
2
Address setup time
t AS
0
—0
—
ns
3
Address valid to end of write
t AW
80 — 85 — ns
Write pulse width
t WP
60
—
70
—
ns
1, 9
Write recovery time
t WR
0
—0
—
ns
4
WE to output in high-Z
t WHZ
0
35 0
40
ns
5
Data to write time overlap
tDW
40 — 40 — ns
Data hold from write time
t DH
0
—0
— ns
Output active from end of write
t OW
5
—5
— ns
Output disable to output in high-Z
t OHZ
0
35 0
40
ns
5
Notes: 1. A write occurs during the overlap of a low CS1, and high CS2, and a high WE. A write begins at
the latest transition among CS1 going low,CS2 going high and WE going low. A write ends at the
earliest transition among CS1 going high CS2 going low and WE going high. Time tWP is measured
from the beginning of write to the end of write.
2. tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
5. During this period, I/O pins are in the output state, therefore the input signals of the opposite phase
to the outputs must not be applied.
6. If CS1 goes low simultaneously with WE going low after WE goes low, the outputs remain in high
impedance state.
7. Dout is the same phase of the written data in this write cycle.
8. Dout is the read data of the next address
9. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
data bus contention
tWP ≥ tWHZ max + tDW min.
9
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