HM6264BLP 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics

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HM6264BLP

64 k SRAM (8-kword × 8-bit)

Hitachi -> Renesas Electronics 

HM6264B Series

Write Timing Waveform (2) (OE Low Fixed) (OE = VIL)

tWC

Address

CS1

Valid address

tAW

tWR

tCW

*1

CS2

WE

Dout

Din

tAS

High Impedance

tWP

tWHZ

tOH

tOW

*2

*3

tDW

tDH

*4

Valid data

Notes:

1. If CS1 goes low simultaneously with WE going low or after WE goes low, the outputs

remain in high impedance state.

2. Dout is the same phase of the written data in this write cycle.

3. Dout is the read data of the next address.

4. If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Input

signals of opposite phase to the outputs must not be applied to I/O pins.

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