HMP9701 데이터 시트보기 (PDF) - Intersil
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HMP9701 Datasheet PDF : 20 Pages
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HMP9701
Input Audio Slot 2: Status Data
Input Audio Slot 6: Microphone Record Channel
This slot delivers control register read data.
TABLE 6. BIT MAP FOR SLOT 1: STATUS DATA
BITS DESCRIPTION
COMMENT
19:4 Control Register Stuffed with 0’s if slot tagged invalid
Read Data
3:0 Reserved
Stuffed with 0’s
Input Audio Slot 3: PCM Record Left Channel
This slot contains an audio sample captured by the left chan-
nel ADC. The resolution of the ADC is 16 bits and is MSB
justified in the 20-bit slot.
TABLE 7. BIT MAP FOR SLOT 3: LEFT CHANNEL RECORD DATA
This slot contains an audio sample captured by the dedi-
cated microphone ADC. The resolution of the ADC is 16 bits
and is MSB justified in the 20-bit slot. This input allows
higher performance echo cancellation algorithms in speaker
phone applications.
TABLE 9. BIT MAP FOR SLOT 6: MICROPHONE RECORD DATA
BITS
DESCRIPTION
COMMENT
19:4 PCM Record Sample
Microphone Channel
16-Bit Audio Sample From
Dedicated Microphone ADC
3:0 Reserved
Stuffed with 0’s
Slots 5, 7-12: Reserved
Audio input slots 5, and 7-12 are reserved, and they are set
to “0”.
BITS
DESCRIPTION
COMMENT
19:4 PCM Record Sample 16-Bit audio sample from Left
Left Channel
Record ADC
3:0 Reserved
Stuffed with 0’s
Input Audio Slot 4: PCM Record Right Channel
This slot contains an audio sample captured by the right
channel ADC. The resolution of the ADC is 16 bits and is
MSB justified in the 20-bit slot.
Low Power Modes
The HMP9701 may be put in a programmable powerdown state
to reduce power when no activity is required. The state of pow-
erdown is controlled by the Powerdown Register (26h). This
register provides 6 commands to powerdown various sections
of the HMP9701. A summary of the power down commands is
given in Table 10 with a more complete description given in the
Control Register Section. Note, the HMP9701 is a fully static
design which will preserve the contents of the internal control
registers if the internal clock is stopped.
TABLE 8. BIT MAP FOR SLOT 4: RIGHT CHANNEL RECORD DATA
BITS
DESCRIPTION
COMMENT
19:4 PCM Record Sample 16-Bit audio sample from Right
Right Channel
Record ADC
3:0 Reserved
Stuffed with 0’s
TABLE 10. SUMMARY OF POWERDOWN REGISTER (26H)
BIT
FUNCTION
PR0 Input Mux and ADC Powerdown
PR1 DAC Powerdown
PR2 Analog Mixer Powerdown (VREF On)
PR3 Analog Mixer Powerdown (VREF Off)
PR4 Digital Interface (AC-Link) Powerdown (External CLK Off)
PR5 Internal CLK Disable
TAG PHASE
20.8µs
(48kHz)
DATA PHASE
SYNC
BIT_CLK
12.288MHz
81.4ns
SDATA_IN
SLOT SLOT
1
2
SLOT
12
“0”
“0”
CODEC
READY
TIME SLOT “VALID” BITS
(“1” = TIME SLOT CONTAINS VALID DATA)
“1” = AC LINK INTERFACE
IS FUNCTIONAL
“0” BIT 19
BIT 0 BIT 19
BIT 0 BIT 19
BIT 0
SLOT 1
SLOT 2
SLOT 12
FIGURE 6. AC LINK AUDIO INPUT FRAME
6
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