HSP-EVAL 데이터 시트보기 (PDF) - Intersil

부품명

상세내역

제조사

HSP-EVAL

DSP Evaluation Platform

Intersil 

HSP-EVAL

Getting Started

The HSP-EVAL was designed to operate in conjunction with

daughter boards designed for the HSPXXXXX family of DSP

products. A simple procedure for assembly and operation of

the target daughter board with the HSP-EVAL is described in

the respective daughter board’s User’s Manual. What follows

in this document is a detailed description of the HSP-EVAL

and its operation.

Bus Structure

The HSP-EVAL utilizes a series of 16-bit busses for daughter

board input, output and control as shown in Figure 1. The

input and output busses interface the daughter board to the

outside world through 96 Pin DIN connectors conforming to

the VME J2/P2 connector standard. Daughter board control is

provided by register driven control busses down loaded with

data via the parallel port of a PC. For added flexibility, the

input busses may also be register driven with down loaded

data.

Two input busses, IN1_0-15 and IN2_0-15, bring data from

the 96 Pin DIN connector (P1) to the daughter board through

the 50 position Input Connector (J1). Each input bus is 16

bits wide and the signal mapping for the above connectors is

given in Tables 1 and 3. As an alternative, the input busses

may be driven by registers which have been down loaded

with data through the Parallel Port Bus.

Two output busses, OUT1_0-15 and OUT2_0-15, carry

daughter board output from the 50 Pin Output Connector

(J2) to the 96 Pin DIN connector (P2). Each output bus is 16

bits wide and the signal mapping for the above connectors is

given in Tables 2 and 4. A shift register is provided to

serialize data on the output busses for transmission via the

Parallel Port Bus.

A status bus, STAT0-3, maps four status outputs from the

daughter board Output Connector J2 to the Configuration

Jumper Field (J4). The Configuration Jumper Field is used to

select one of the four status lines for transmission via the

Parallel Port Bus (see Configuration Jumper Field Section).

The two control busses, IN3_0-15 and CTL0-15, connect a

set of registers to the 50 Pin Control Connector (J3). Each

control bus is 16 bits wide and the signal mapping for the J3

Control Connector is shown in Table 5. The four least

significant bits of the CTL0-15 bus are also used to control

the operation of the HSP-EVAL (see Register Structure

Section). As with the registers driving the input busses, the

registers driving the control busses are down loaded with

data via the Parallel Port Bus.

Parallel Port Bus

The Parallel Port Bus carries the data and signals required

to support bidirectional data transfers between the HSP-

EVAL and the parallel port of an IBM PC or compatible. The

port bus contains eight data lines, PCD0-7, two control lines,

PCWR0-1, and three serial output lines, PCRD0-2. The con-

trol and data lines are used to down load data into the HSP-

EVAL's on board registers via the Parallel Port Interface. The

serial output lines carry daughter board status and output

serialized by the On Board Shift Register.

INPUT BUS 1

16

(IN1_0-15)

INPUT BUS 2

16

(IN2_0-15)

CLK IN

INPUT

REG 1

INPUT

REG 2

CONTROL CONNECTOR

(J3)

16

16

CTL0

CTL2-3

INPUT

REG 3

CTL CONTROL

REG

OUTPUT BUS 1

(OUT1_0-15)

OUTPUT BUS 2

(OUT2_0-15)

16

16

CLK OUT

SHIFT REGISTER

PARALLEL PORT

INTERFACE

EXT CLK

OSC

PARALLEL PORT BUS

CLK ADDRESS OUTPUT OUTPUT

SELECT SELECT ENABLE SELECT

CONFIGURATION JUMPER FIELD (J4)

13

SHROUDED HEADER

(J5)

26 PIN HEADER

FIGURE 1. BLOCK DIAGRAM OF HSP-EVAL

2

Share Link: