HSP-EVAL 데이터 시트보기 (PDF) - Intersil
부품명
상세내역
제조사
HSP-EVAL Datasheet PDF : 12 Pages
| |||
HSP-EVAL
The registers driving the control and input busses may be
three-stated when it is desired to drive those busses through
the 96 Pin Input Connector or headers on the target
daughter board. The registers driving a particular bus are
three-stated by removing the respective Output Enable
jumper in the J4 Configuration Jumper Field (see
Configuration Jumper Field).
The HSP-EVAL's two 16-bit output busses can be serialized
by a 32-bit shift register for reading via the Parallel Port Bus.
The CTL Control Register governs the loading and clocking
of data out of the shift register. The mapping of this register
to the output busses is shown in Table 8.
TABLE 5. SIGNAL ASSIGNMENTS FOR 50 POSITION
CONTROL CONNECTOR J3
PIN
NUMBER
J3A SIGNAL
MNEMONIC
J3B SIGNAL
MNEMONIC
1
N.C.
GND
2
IN3_0
IN3_1
3
IN3_2
IN3_3
4
IN3_4
IN3_5
5
IN3_6
IN3_7
6
GND
IN3_8
7
IN3_9
IN3_10
8
IN3_11
IN3_12
9
IN3_13
IN3_14
10
IN3_15
GND
11
N.C.
CTL0
12
CTL1
CTL2
13
CTL3
CTL4
14
CTL5
CTL6
15
CTL7
GND
16
CTL8
CTL9
17
CTL10
CTL11
18
CTL12
CTL13
19
CTL14
CTL15
20
GND
N.C.
21
GND
N.C.
22
GND
N.C.
23
GND
N.C.
24
GND
N.C.
25
GND
N.C.
Down Loading Data via Parallel Port
Interface
The four “logical” control and input registers are down loaded
by a series of single byte writes to the to the Parallel Port
Interface. The Parallel Port Interface consists of two
decoders, an 8-bit address register, and an 8-bit holding
register. The on-board registers are down loaded by first
writing data to the Parallel Port Interface's holding register
followed by two writes to the Interface's Address Register. By
writing the address register, data in the holding register is
loaded into one of the eight registers on-board the HSP-
EVAL. The address register specifies the particular register
for loading, as well as the board address of the HSP-EVAL
targeted for the data download. The HSP-EVAL board
address is selected in the J4 Jumper Field (see
Configuration Jumper Field Section), and the memory map
for the 8 data registers is shown in Table 7. The bit map for
the Parallel Port Interface’s Address Register is given in
Table 9.
The Parallel Port Interface's address and holding registers
are loaded with data from the PCD0-7 data lines of the
Parallel Port Bus by a “low” to “high” transition on the
appropriate bus control line. Specifically, the Interface's
Address Register is loaded with data when a “low” to “high”
transition occurs on the PCWR0 line of the Parallel Port Bus,
and the holding register is loaded by a like transition on the
PCWR1 line. The mapping of the Parallel Port Bus signals
mentioned above to the PC's parallel port is given in Table 6.
TABLE 6. SIGNAL MAPPING SFOR 27 PIN SHROUDED
HEADER J5
PIN
NUMBER
J6A SIGNAL
MNEMONIC
J6B SIGNAL
MNEMONIC
1
N.C.
N.C.
2
PCD0 (D0)
N.C.
3
PCD1 (D1)
PCWR0 (INIT
PRINTER)
4
PCD2 (D2)
PCWR1 (SELECT
IN)
5
PCD3 (D3)
GND
6
PCD4 (D4)
GND
7
PCD5 (D5)
GND
8
PCD6 (D6)
GND
9
PCD7 (D7)
GND
10
N.C.
GND
11
PCRD0 (BUSY)
GND
12
PCRD2 (PAPER
GND
END)
13
PCRD1 (SELECT) GND
NOTE: BM PC compatible parallel port signals are shown in
parenthesis.
5
Share Link: 