HSP50214 데이터 시트보기 (PDF) - Intersil

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HSP50214

Programmable Downconverter

Intersil 

HSP50214

For example, if N is 3267 (decimal), and fIN is 52MHz, then

FC is 39.55Hz. If received data is modulated at a carrier fre-

quency of 10MHz, then the synthesizer/mixer should be pro-

grammed for N = 313B13B1 (hex) or CEC4EC4F(hex).

would produce a phase offset of 11.25o and a value of -512

would produce an offset of 180o. The phase offset is loaded via

the microprocessor interface. See the Microprocessor Write

Section on instructions for writing Control Word 4.

Because the input enable, ENI, controls the operation of the

phase accumulator, the NCO output frequency is computed

relative to the input sample rate, fIN, not to fCLKIN. The fre-

quency control, N, is interpreted as two’s complement

because the output of the NCO is quadrature. Negative fre-

quency L.O.s select the upper sideband; positive frequency

L.O.s select the lower sideband. The range of the NCO is -

fIN/2 to +fIN/2. The frequency resolution of the NCO is

fIN/(232) or approximately 0.012Hz when CLKIN is 52 MSPS

and ENI is tied low.

TO MIXERS

COS

SIN

18 18

REG

REG

SIN/COS

ROM

CARRIER

PHASE

STROBE†

18

10 R R

+

EE

GG

CARRIER

PHASE

OFFSET †

PHASE

ACCUMULATOR

ENI

REG

0

R

MUX

E

G

CLEAR

PHASE

ACCUM †

COF

ENABLE †

MUX

32

COF

0

REG

+

32

CF

CARRIER

FREQUENCY

STROBE †

COFSYNC

COF

SYNCIN1

SYNC

SHIFT REG

SYNC

CIRCUITRY

REG

REG

CARRIER

FREQUENCY†

CARRIER

LOAD ON

UPDATE†

† Controlled via microprocessor interface.

FIGURE 12. BLOCK DIAGRAM OF NCO SECTION

The phase of the Carrier NCO can be shifted by adding a

10-bit phase offset to the MSB’s (modulo 360o) of the output

of the phase accumulator. This phase offset control has a

resolution of 0.35o and can be interpreted as two’s comple-

ment from -180o to 180o (-π to π) or as binary from 0 to

360o (0 to 2π). The phase offset is given by:

φOFF = 2π × (PO ⁄ 210);(–(29 – 1) < PO < (29 – 1))

or, in terms of the parameter to be programmed:

PO = INT[(210φOFF) ⁄ 2π ]HEX;(–π < φOFF < π)

(EQ. 4)

(EQ. 4A)

The most significant 18 bits from the phase adder are used

as the address a sin/cos look-up table. This look-up table

maps phase into sinusoidal amplitude. The sine and cosine

values have 18 bits of amplitude resolution. The spurious

components in the sine/cosine generation are at least

-96dBc. The sine and cosine samples are routed to the

mixer section whSere they are multiplied with the input sam-

ples to translate the signal of interest to baseband.

The mixer multiplies the 14-bit input by the 18-bit quadrature

sinusoids. The mixer equations are:

IOUT = IIN × cos (ωc)

(EQ. 5)

QOUT = IIN × sin (ωc)

(EQ. 5A)

The mixer output is rounded symmetrically to 15 bits.

To allow the frequency and phase of multiple parts to be

updated synchronously, two sets of registers are used for

latching the center frequency and phase offset words. The

offset phase and center frequency control words are first

loaded into holding registers. The contents of the holding

registers are transferred to active registers in one of two

ways. The first technique involves writing to a specific Con-

trol Word Address. A processor write to Control Word 5,

transfers the center frequency value to the active register

while a processor write to Control Word 6 transfers the

phase offset value to the active register.

The second technique, designed for synchronizing updates

to multiple parts, uses the SYNCIN1 pin to update the active

registers. When Control Word 1, bit 20 is set to 1, the

SYNCIN1 pin causes both the center frequency and phase

offset holding registers to be transferred to active registers.

Additionally, when Control Word 0, bit 0 is set to 1, the feed-

back in the phase accumulator is zeroed when the transfer

from the holding to active register occurs. This feature pro-

vides synchronization of the phase accumulator starting

phase of multiple parts. It can also be used to reset the

phase of the NCO synchronous with a specific event.

The carrier offset frequency is loaded using the COF and

COFSYNC pins. Figure 13 details the timing relationship

between COF, COFSYNC and CLKIN. The offset frequency

word can be zeroed if it is not needed. Similarly, the

Sample Offset Frequency register controlling the resampler

NCO is loaded via the SOF and SOFSYNC pins. The

procedure for loading data through the two pin NCO

interfaces is identical except that the timing of SOF and

SOFSYNC is relative to PROCCLK.

where PO is the 10-bit two’s complement value loaded into the

Phase Offset register (Control Word 4, bits 9-0). For example, a

value of 32 (decimal) loaded into the Phase Offset register

12

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