HT47C20-1 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT47C20-1 Datasheet PDF : 41 Pages
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from the stack. After a chip reset, the SP will point to the
top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent four return ad-
dresses are stored).
Data Memory - RAM
The data memory is designed with 85´8 bits. The data
memory and is divided into two functional groups: spe-
cial function registers and general purpose data mem-
ory (64´8). Most are read/write, but some are read only.
The special function registers include the indirect ad-
dressing register 0 (00H), the memory pointer register 0
(mp0; 01H), the indirect addressing register 1 (02H), the
memory pointer register 1 (MP1;03H), the bank pointer
(BP;04H), the accumulator (ACC;05H), the program
counter lower-order byte register (PCL;06H), the table
pointer (TBLP;07H), the table higher-order byte register
(TBLH;08H), the real time clock control register
(RTCC;09H), the status register (STATUS;0AH), the in-
terrupt control register 0 (INTC0;0BH), the I/O registers
(PA;12H, PB;14H), the interrupt control register 1
(INTC1;1EH), the timer/event counter A higher order byte
register (TMRAH;20H), the timer/event counter A lower or-
der byte register (TMRAL;21H), the timer/event counter
control register (TMRC;22H), the timer/event counter B
higher order byte register (TMRBH;23H), the timer/event
counter B lower order byte register (TMRBL;24H), and the
RC oscillator type A/D converter control register (ADCR;
25H). The remaining space before the 40H are reserved
for future expanded usage and reading these location
will return the result 00H. The general purpose data
memory, addressed from 40H to 7FH, is used for data
and control information under instruction command.
All data memory areas can handle arithmetic, logic, in-
crement, decrement and rotate operations. Except for
some dedicated bits, each bit in the data memory can be
set and reset by the SET [m].i and CLR [m].i instruction,
respectively. They are also indirectly accessible through
memory pointer registers (MP0;01H, MP1;03H).
HT47R20A-1/HT47C20-1
0 0 H In d ir e c t A d d r e s s in g R e g is te r 0
01H
MP 0
0 2 H In d ir e c t A d d r e s s in g R e g is te r 1
03H
M P1
04H
BP
05H
ACC
06H
PCL
07H
TB LP
08H
TB LH
09H
R TC C
0A H
STATU S
0B H
IN T C 0
0C H
0D H
0E H
0FH
10H
11H
12H
PA
13H
14H
PB
15H
16H
17H
18H
19H
1A H
1B H
1C H
1D H
1E H
IN T C 1
1FH
20H
TM R AH
21H
TM R AL
22H
TM R C
23H
TM R BH
24H
TM R BL
25H
ADCR
26H
40H
S p e c ia l P u r p o s e
D a ta M e m o ry
:U nused
R e a d a s "0 0 "
G e n e ra l P u rp o s e
D a ta M e m o ry
(6 4 B y te s )
7FH
RAM Mapping (Bank 0)
Rev. 1.80
9
June 23, 2008
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