HT48RA0-2 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT48RA0-2 Datasheet PDF : 32 Pages
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HT48RA0-2/HT48CA0-2
D.C. Characteristics
Symbol
Parameter
Test Conditions
VDD
Conditions
VDD
Operating Voltage
¾
¾
IDD
Operating Current
3V No load, fSYS=4MHz
ISTB
Standby Current
3V No load, system HALT
VIL1
Input Low Voltage for I/O Ports 3V
¾
VIH1
Input High Voltage for I/O Ports 3V
¾
VIL2
Input Low Voltage (RES)
3V
¾
VIH2
Input High Voltage (RES)
3V
¾
VLVR Low Voltage Reset Voltage
¾
¾
IOL
I/O Ports Sink Current
3V VOL=0.1VDD
IOH
PC0/REM Output Source Current 3V VOH=0.9VDD
RPH
Pull-high Resistance
3V
¾
Ta=25°C
Min. Typ. Max. Unit
2.0
¾
3.6
V
¾
0.7 1.5 mA
¾
¾
1
mA
0
¾ 0.3VDD V
0.7VDD ¾
VDD
V
0
¾ 0.4VDD V
0.9VDD ¾
VDD
V
¾
1.9 2.0
V
4
8
¾
mA
-2
-4
¾
mA
20
60 100 kW
A.C. Characteristics
Ta=25°C
Symbol
Parameter
fSYS
System Clock
tRES
External Reset Low Pulse Width
tSST
System Start-up Timer Period
tLVR
Low Voltage Width to Reset
Test Conditions
VDD
Conditions
3V
¾
¾
¾
¾
Power-up, reset or wake-up
from HALT
¾
¾
Min.
400
1
¾
1
Typ.
¾
¾
1024
¾
Max.
4000
¾
¾
¾
Unit
kHz
ms
tSYS
ms
Note: tSYS=1/fSYS
Functional Description
Execution Flow
The HT48RA0-2/HT48CA0-2 system clock can be de-
rived from a crystal/ceramic resonator oscillator. It is in-
ternally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
T1 T2 T3 T4 T1
S y s te m C lo c k
In s tr u c tio n C y c le
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute within one cycle. If an instruc-
tion changes the program counter, two cycles are
required to complete the instruction.
T2 T3 T4 T1 T2 T3 T4
PC
PC
PC +1
PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
Execution Flow
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Rev. 1.50
3
July 23, 2004
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