HT48RA0-3 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT48RA0-3

Remote Type 8-Bit MCU

Holtek Semiconductor 

HT48RA0-3/HT48CA0-3

Power Down Operation - HALT

The Power-down mode is initialised by the HALT in-

struction and results in the following:

· The system oscillator turns off and the WDT stops.

· The contents of the on-chip Data Memory and regis-

ters remain unchanged.

· WDT prescaler is cleared.

· All I/O ports maintain their original status.

· The PDF flag is set and the TO flag is cleared.

The system can quit the HALT mode by means of an ex-

ternal falling edge signal on port B. By examining the TO

and PDF flags, the reason for chip reset can be deter-

mined. The PDF flag is cleared when the system powers

up or when a CLR WDT instruction is executed and is set

when the HALT instruction is executed. The TO flag is set

if the WDT time-out occurs during normal operation.

The port B wake-up can be considered as a continuation

of normal execution. Each bit in port B can be independ-

ently selected to wake up the device by the code option.

Awakening from an I/O port stimulus, the program will

resume execution of the next instruction.

Once a wake-up event(s) occurs, it takes 1024 tSYS

(system clock periods) to resume normal operation. In

other words, a dummy cycle period will be inserted after

the wake-up.

To minimize power consumption, all I/O pins should be

carefully managed before entering the HALT status.

Reset

There are three ways in which a reset can occur:

· Power On reset

· Low Voltage reset

· WDT time-out reset during normal operation

VDD

P o w e r-o n R e s e t

S S T T im e - o u t

In te rn a l R e s e t

tR S T D

Reset Timing Chart

Some registers remain unchanged during reset condi-

tions. Most registers are reset to the ²initial condition²

when the reset conditions are met. By examining the

PDF and TO flags, the program can distinguish between

different chip resets.

TO PDF

RESET Conditions

0 0 Power-on reset during power-up

u u LVR reset during normal operation

1 u WDT time-out during normal operation

Note: ²u² means unchanged.

To guarantee that the system oscillator has started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem powers up or when the system awakes from a HALT

state.

When a system power up occurs, an SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

The functional unit chip reset status is shown below.

Program Counter

WDT Prescaler

Input/Output ports

Stack Pointer

Carrier output

000H

Clear

Input mode

Points to the top of the stack

Low level

H A LT

W DT

LV R

O SC1

SST

1 0 -s ta g e

R ip p le C o u n te r

P o w e r - o n D e te c tio n

Reset Configuration

C o ld R e s e t

Rev.1.10

8

October 12, 2007

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