HT48R03 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT48R03

10-Pin MSOP I/O Type 8-Bit OTP MCU

Holtek Semiconductor 

HT48R01/HT48R02/HT48R03

The internal timer/event counter interrupt is initialised by

setting the timer/event counter interrupt request flag

(TF; bit 5 of INTC), caused by a timer overflow. When

the interrupt is enabled, the stack is not full and the TF

bit is set, a subroutine call to location 08H will occur. The

related interrupt request flag,TF, will be reset and the

EMI bit cleared to disable further interrupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are held until the ²RETI²

instruction is executed or the EMI bit and the related in-

terrupt control bit are set to 1 (of course, if the stack is

not full). To return from the interrupt subroutine, ²RET²

or ²RETI² may be invoked. RETI will set the EMI bit to en-

able an interrupt service, but RET will not.

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

Interrupt Source

Priority Vector

External Interrupt

1

04H

Timer/Event Counter 0 Overflow 2

08H

Interrupt Subroutine Vector for HT48R01

Interrupt Source

Priority Vector

External Interrupt

1

04H

Timer/Event Counter 0 Overflow 2

08H

Timer/Event Counter 1 Overflow 3

0CH

Interrupt Subroutine Vector for HT48R02/HT48R03

Once the interrupt request flags (T0F/ T1F, EIF) are set,

they will remain in the INTC register until the interrupts

are serviced or cleared by a software instruction. It is

recommended that a program does not use the ²CALL

subroutine² within the interrupt subroutine. Interrupts

often occur in an unpredictable manner or need to be

serviced immediately in some applications. If only one

stack is left and enabling the interrupt is not well con-

trolled, the original control sequence will be damaged

once the ²CALL² operates in the interrupt subroutine.

Oscillator Configuration

There are 4 different oscillator modes implemented in

the microcontroller, which are selected by configuration

options. All of them are designed for system clocks,

namely the external RC oscillator (ERC), external crys-

tal oscillator (ECRY), internal RC oscillator with I/O(IRC)

and internal RC oscillator with RTC OSC (IRC+RTC).

No matter what oscillator type is selected, the signal

provides the system clock. The Power-down mode

stops the system oscillator, except for the RTC oscilla-

tor, and resists external signals to conserve power.

Bit No.

0

1

2

3, 6~7

4

5

Label

EMI

EEI

ET0I

¾

EIF

T0F

Function

Controls the master (global) interrupt (1= enabled; 0= disabled)

Controls the external interrupt (1= enabled; 0= disabled)

Controls the timer/event counter 0 interrupt (1= enabled; 0= disabled)

Unused bit, read as ²0²

External interrupt request flag (1= active; 0= inactive)

Internal timer/event counter 0 request flag (1= active; 0= inactive)

INTC 0 (0BH) Register for HT48R01

Bit No.

0

1

2

3

4

5

5

7

Label

EMI

EEI

ET0I

ET1I

EIF

T0F

T1F

¾

Function

Controls the master (global) interrupt (1= enabled; 0= disabled)

Controls the external interrupt (1= enabled; 0= disabled)

Controls the timer/event counter 0 interrupt (1= enabled; 0= disabled)

Controls the timer/event counter 1 interrupt (1= enabled; 0= disabled)

External interrupt request flag (1= active; 0= inactive)

Internal timer/event counter 0 request flag (1= active; 0= inactive)

Internal timer/event counter 1 request flag (1= active; 0= inactive)

Unused bit, read as ²0²

INTC 0 (0BH) Register for HT48R02/HT48R03

Rev. 1.00

11

December 20, 2006

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