HT48C062(2006) 데이터 시트보기 (PDF) - Holtek Semiconductor
부품명
상세내역
제조사
HT48C062 Datasheet PDF : 31 Pages
| |||
HT48R062/HT48C062
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H or 14H)
instructions.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of Port A has the capability of waking-up the
device. The highest 5-bit of Port B are not physically im-
plemented; on reading them a ²0² is returned whereas
writing then results in a no-operation. See Application
note.
There are pull-high options available for PA and PB.
Once the pull-high option is selected, I/O lines have
pull-high resistors. Otherwise, the pull-high resistors are
absent. It should be noted that a non-pull-high I/O line
operating in input mode will cause a floating state.
Low Voltage Reset - LVR
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will au-
tomatically reset the device internally.
The LVR includes the following specifications:
· The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
· The LVR uses the ²OR² function with the external
RES signal to perform chip reset.
The relationship between VDD and VLVR is shown below.
V DD
V O PR
5 .5 V 5 .5 V
V LV R
3 .0 V
2 .2 V
V DD
5 .5 V
V LV R
0 .9 V
0V
R e s e t S ig n a l
Note:
0 .9 V
VOPR is the voltage range for proper chip opera-
tion at 4MHz system clock.
L V R D e te c t V o lta g e
R eset
N o r m a l O p e r a tio n
R eset
*1
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters
the reset mode.
Rev. 1.11
10
October 30, 2006
Share Link: 