HT48R062(2006) 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT48R062
(Rev.:2006)

Cost-Effective I/O Type 8-Bit MCU

Holtek Semiconductor 

HT48R062/HT48C062

struction. The software instruction include ²CLR WDT²

and the other set - ²CLR WDT1² and ²CLR WDT2². Of

these two types of instruction, only one can be active de-

pending on the option - ²CLR WDT times selection op-

tion². If the ²CLR WDT² is selected (i.e. CLRWDT times

equal one), any execution of the ²CLR WDT² instruction

will clear the WDT. In the case that ²CLR WDT1² and

²CLR WDT2² are chosen (i.e. CLRWDT times equal

two), these two instructions must be executed to clear

the WDT; otherwise, the WDT may reset the chip as a

result of time-out.

Power Down Operation - HALT

The HALT mode is initialized by the ²HALT² instruction

and results in the following...

· The system oscillator turns off and the WDT stops.

· The contents of the on-chip RAM and registers remain

unchanged.

· WDT prescaler are cleared.

· All I/O ports maintain their original status.

· The PDF flag is set and the TO flag is cleared.

The system can quit the HALT mode by means of an ex-

ternal reset or an external falling edge signal on port B.

An external reset causes a device initialization. Exam-

ining the TO and PDF flags, the reason for chip reset

can be determined. The PDF flag is cleared when the

system powers up or execute the ²CLR WDT² instruc-

tion and is set when the ²HALT² instruction is executed.

The TO flag is set if the WDT time-out occurs, and

causes a wake-up that only resets the program counter

and SP, the others keep their original status.

The Port A wake-up can be considered as a continua-

tion of normal execution. Each bit in Port A can be inde-

pendently selected to wake up the device by the code

option. Awakening from an I/O port stimulus, the pro-

gram will resume execution of the next instruction.

Once a wake-up event(s) occurs, it takes 1024 tSYS

(system clock period) to resume normal operation. In

other words, a dummy cycle period will be inserted after

the wake-up.

To minimize power consumption, all I/O pins should be

carefully managed before entering the HALT status.

Reset

There are three ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

Some registers remain unchanged during reset condi-

tions. Most registers are reset to the ²initial condition²

when the reset conditions are met. By examining the

PDF and TO flags, the program can distinguish between

different ²chip resets².

TO PDF

RESET Conditions

0 0 RES reset during power-up

u u RES reset during normal operation

0 1 RES wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² means unchanged.

To guarantee that the system oscillator has started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem powers up or when the system awakes from a HALT

state.

When a system power up occurs, an SST delay is added

during the reset period. But when the reset comes from

the RES pin, the SST delay is disabled. Any wake-up

from HALT will enable the SST delay.

The functional unit chip reset status is shown below.

Program Counter

WDT Prescaler

Input/Output ports

Stack Pointer

000H

Clear

Input mode

Points to the top of the stack

VDD

RES

S S T T im e - o u t

C h ip R e s e t

tS S T

Reset Timing Chart

V DD

RES

Reset Circuit

H A LT

W DT W DT

T im e - o u t

R eset

RES

O SC1

SST

1 0 -s ta g e

R ip p le C o u n te r

P o w e r - o n D e te c tio n

Reset Configuration

R eset

Rev. 1.11

8

October 30, 2006

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